diff options
| author | Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> | 2017-08-25 20:39:14 +0300 |
|---|---|---|
| committer | Stephen Boyd <sboyd@codeaurora.org> | 2017-08-30 22:36:05 -0700 |
| commit | daeeb438c052e3763617c636943e07a8f3684e9e (patch) | |
| tree | 5db2bde1740022066098ae70919e7a14093a4e22 /drivers/clk/Kconfig | |
| parent | 59273246b2df45feaea05e1069914f8ec2120c8c (diff) | |
ARC: clk: introduce HSDK pll driver
HSDK board manages its clocks using various PLLs. These PLL have same
dividers and corresponding control registers mapped to different addresses.
So we add one common driver for such PLLs.
Each PLL on HSDK board consists of three dividers: IDIV, FBDIV and
ODIV. Output clock value is managed using these dividers.
We add pre-defined tables with supported rate values and appropriate
configurations of IDIV, FBDIV and ODIV for each value.
As of today we add support for PLLs that generate clock for the
HSDK arc cpus, system, ddr, AXI tunnel and hdmi.
By this patch we add support for several plls (arc cpus pll and others),
so we had to use two different init types: CLK_OF_DECLARE for arc cpus pll
and regular probing for others plls.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Reviewed-by: Vineet Gupta <vgupta@synopsys.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/Kconfig')
| -rw-r--r-- | drivers/clk/Kconfig | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index a874b72612d0..fdc99082a343 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -31,6 +31,13 @@ config COMMON_CLK_WM831X source "drivers/clk/versatile/Kconfig" +config CLK_HSDK + bool "PLL Driver for HSDK platform" + depends on OF || COMPILE_TEST + ---help--- + This driver supports the HSDK core, system, ddr, tunnel and hdmi PLLs + control. + config COMMON_CLK_MAX77686 tristate "Clock driver for Maxim 77620/77686/77802 MFD" depends on MFD_MAX77686 || MFD_MAX77620 || COMPILE_TEST |