diff options
| author | Wen He <wen.he_1@nxp.com> | 2019-12-13 16:34:02 +0800 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2020-01-30 16:28:07 -0800 |
| commit | d37010a3c162f23e47a11a8f5946dbd974999c42 (patch) | |
| tree | c88cfd4d84af3241ddfd743948f6b432aead903a /drivers/clk/Kconfig | |
| parent | 87a5ffb34b475263c3f3d187f776d77178be8eb9 (diff) | |
clk: ls1028a: Add clock driver for Display output interface
Add clock driver for QorIQ LS1028A Display output interfaces(LCD, DPHY),
as implemented in TSMC CLN28HPM PLL, this PLL supports the programmable
integer division and range of the display output pixel clock's 27-594MHz.
Signed-off-by: Wen He <wen.he_1@nxp.com>
Signed-off-by: Michael Walle <michael@walle.cc>
Link: https://lkml.kernel.org/r/20191213083402.35678-2-wen.he_1@nxp.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/Kconfig')
| -rw-r--r-- | drivers/clk/Kconfig | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 45653a0e6ecd..32943544b446 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -225,6 +225,16 @@ config CLK_QORIQ This adds the clock driver support for Freescale QorIQ platforms using common clock framework. +config CLK_LS1028A_PLLDIG + tristate "Clock driver for LS1028A Display output" + depends on ARCH_LAYERSCAPE || COMPILE_TEST + default ARCH_LAYERSCAPE + help + This driver support the Display output interfaces(LCD, DPHY) pixel clocks + of the QorIQ Layerscape LS1028A, as implemented TSMC CLN28HPM PLL. Not all + features of the PLL are currently supported by the driver. By default, + configured bypass mode with this PLL. + config COMMON_CLK_XGENE bool "Clock driver for APM XGene SoC" default ARCH_XGENE |