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| author | Stephen Boyd <sboyd@kernel.org> | 2019-07-12 11:07:23 -0700 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2019-07-12 11:07:23 -0700 |
| commit | 55692cedf3af29039381e3dbf1b598ab21709d1e (patch) | |
| tree | 74c172fedb11e81f899b4729ef36f0145b161bf8 /drivers/clk/Kconfig | |
| parent | a188339ca5a396acc588e5851ed7e19f66b0ebd9 (diff) | |
| parent | 794e94ca83450c436313df18291e139cf5f9121f (diff) | |
Merge tag 'v5.3-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-rockchip
Pull Rockchip clk driver updates from Heiko Stuebner:
- New clock-ids+exports for two clocks
- Cleanup for some boilerplate code for clocks we cannot really control
from the kernel, but want to define separately to match the
hardware-description (watchdog in secure-grf)
- Improvement in mmc phase calculation and cleanup of some rate defintions
* tag 'v5.3-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
clk: rockchip: export HDMIPHY clock on rk3228
clk: rockchip: add watchdog pclk on rk3328
clk: rockchip: add clock id for hdmi_phy special clock on rk3228
clk: rockchip: add clock id for watchdog pclk on rk3328
clk: rockchip: convert pclk_wdt boilerplat to new SGRF_GATE macro
clk: rockchip: add a type from SGRF-controlled gate clocks
clk: rockchip: Remove 48 MHz PLL rate from rk3288
clk: rockchip: add 1.464GHz cpu-clock rate to rk3228
clk: rockchip: Slightly more accurate math in rockchip_mmc_get_phase()
clk: rockchip: Don't yell about bad mmc phases when getting
clk: rockchip: Use clk_hw_get_rate() in MMC phase calculation
Diffstat (limited to 'drivers/clk/Kconfig')
0 files changed, 0 insertions, 0 deletions