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authorRadhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>2019-10-22 22:30:22 +0530
committerVinod Koul <vkoul@kernel.org>2019-11-06 22:38:02 +0530
commit6ccd692bfb7fc44a6b4acd97874d8be78ecb5c91 (patch)
tree58a37ed16bd73b3d0ccd1bb7b7500cc937720691 /drivers/bus
parentc2f6b67db2bd2c333ccd30099c9bde197fa3943d (diff)
dmaengine: xilinx_dma: Add Xilinx AXI MCDMA Engine driver support
Add support for AXI Multichannel Direct Memory Access (AXI MCDMA) core, which is a soft Xilinx IP core that provides high-bandwidth direct memory access between memory and AXI4-Stream target peripherals. The AXI MCDMA core provides scatter-gather interface with multiple independent transmit and receive channels. The driver supports device_prep_slave_sg slave transfer mode. Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> Link: https://lore.kernel.org/r/1571763622-29281-7-git-send-email-radhey.shyam.pandey@xilinx.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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