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authorArjun Vynipadath <arjun@chelsio.com>2017-03-20 14:22:38 +0530
committerDavid S. Miller <davem@davemloft.net>2017-03-22 10:53:49 -0700
commitbb58d07964f2f09e133b46541447c567a7306dc1 (patch)
tree66f9c4176f5d5228d5e8792da557f2786a95308a /drivers/bcma/driver_chipcommon_pmu.c
parent3588f29e061cef19ac0092e4f6917717fed5b1d4 (diff)
cxgb4: Update IngPad and IngPack values
We are using the smallest padding boundary (8 bytes), which isn't smaller than the Memory Controller Read/Write Size We get best performance in 100G when the Packing Boundary is a multiple of the Maximum Payload Size. Its related to inefficient chopping of DMA packets by PCIe, that causes more overhead on bus. So driver is helping by making the starting address alignment to be MPS size. We will try to determine PCIE MaxPayloadSize capabiltiy and set IngPackBoundary based on this value. If cache line size is greater than MPS or determinig MPS fails, we will use cache line size to determine IngPackBoundary(as before). Signed-off-by: Arjun Vynipadath <arjun@chelsio.com> Signed-off-by: Casey Leedom <leedom@chelsio.com> Signed-off-by: Ganesh Goudar <ganeshgr@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/bcma/driver_chipcommon_pmu.c')
0 files changed, 0 insertions, 0 deletions