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| author | Aravind Gopalakrishnan <aravind.gopalakrishnan@amd.com> | 2015-07-13 06:53:02 -0500 |
|---|---|---|
| committer | Borislav Petkov <bp@suse.de> | 2015-07-14 06:32:53 +0200 |
| commit | 99e1dfb7d2094d9afc1dca57d525f7b36aa18079 (patch) | |
| tree | 0fa79a761aa50d0fad914326d8f9a42bf6bcb64b /crypto | |
| parent | ca12bb14fee138603d17b1d68906abeebaa09b30 (diff) | |
EDAC, mce_amd: Don't emit 'CE' for Deferred error
Currently, when decoding an MCE, we display 'CE' for a Deferred error, like
this:
[Hardware Error]: CPU:0 (15:2:0) MC4_STATUS[Over|CE|MiscV|-|AddrV|Deferred|-|UECC]: 0xdc04b00095080813
When the 'UC' bit in the MCx_STATUS register is clear, the error status
is either a Corrected error or Deferred error as determined by the
'Deferred' bit. So do not print 'CE' on a deferred error.
Refer to AMD Error Scope Hierarchy table in a newer BKDG (example:
49125_15h_Models_30h-3Fh_BKDG.pdf, section "RAS Features").
Signed-off-by: Aravind Gopalakrishnan <aravind.gopalakrishnan@amd.com>
Cc: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
Cc: linux-edac <linux-edac@vger.kernel.org>
Link: http://lkml.kernel.org/r/1436788382-6463-1-git-send-email-aravind.gopalakrishnan@amd.com
Signed-off-by: Borislav Petkov <bp@suse.de>
Diffstat (limited to 'crypto')
0 files changed, 0 insertions, 0 deletions