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author | Ludovic Barre <ludovic.barre@st.com> | 2018-04-30 09:11:00 +0200 |
---|---|---|
committer | Alexandre Torgue <alexandre.torgue@st.com> | 2018-05-04 09:45:49 +0200 |
commit | c38928d638f16611ea0534374d212b205976c37a (patch) | |
tree | fe390f458035988fd5ed40a7dcce129d6cd3c009 /arch | |
parent | af8b2cf25c77e9844b764e6db62cb34c75cebd36 (diff) |
ARM: dts: stm32: add qspi support for stm32mp157c
This patch adds qspi support on stm32mp157c,
read in memory mapped, write in indirect mode.
Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/boot/dts/stm32mp157c.dtsi | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi b/arch/arm/boot/dts/stm32mp157c.dtsi index 5ef6495fc2da..203fa972895f 100644 --- a/arch/arm/boot/dts/stm32mp157c.dtsi +++ b/arch/arm/boot/dts/stm32mp157c.dtsi @@ -720,6 +720,16 @@ dma-requests = <48>; }; + qspi: qspi@58003000 { + compatible = "st,stm32f469-qspi"; + reg = <0x58003000 0x1000>, <0x70000000 0x10000000>; + reg-names = "qspi", "qspi_mm"; + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc QSPI_K>; + resets = <&rcc QSPI_R>; + status = "disabled"; + }; + crc1: crc@58009000 { compatible = "st,stm32f7-crc"; reg = <0x58009000 0x400>; |