diff options
| author | Alexander Graf <graf@amazon.com> | 2020-07-01 16:02:06 +0200 |
|---|---|---|
| committer | Marc Zyngier <maz@kernel.org> | 2020-07-05 19:15:34 +0100 |
| commit | 731532176716e2775a5d21115bb9c5c61e0cb704 (patch) | |
| tree | 775100c41586da8f74b890678b7b50a3308968cd /arch | |
| parent | 2da3ffa6e840b9f8fc65a71326c43b716992861d (diff) | |
KVM: arm64: vgic-its: Change default outer cacheability for {PEND, PROP}BASER
PENDBASER and PROPBASER define the outer caching mode for LPI tables.
The memory backing them may not be outer sharable, so we mark them as nC
by default. This however, breaks Windows on ARM which only accepts
SameAsInner or RaWaWb as values for outer cachability.
We do today already allow the outer mode to be set to SameAsInner
explicitly, so the easy fix is to default to that instead of nC for
situations when an OS asks for a not fulfillable cachability request.
This fixes booting Windows in KVM with vgicv3 and ITS enabled for me.
Signed-off-by: Alexander Graf <graf@amazon.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20200701140206.8664-1-graf@amazon.com
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm64/kvm/vgic/vgic-mmio-v3.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm64/kvm/vgic/vgic-mmio-v3.c b/arch/arm64/kvm/vgic/vgic-mmio-v3.c index d2339a2b9fb9..5c786b915cd3 100644 --- a/arch/arm64/kvm/vgic/vgic-mmio-v3.c +++ b/arch/arm64/kvm/vgic/vgic-mmio-v3.c @@ -389,7 +389,7 @@ u64 vgic_sanitise_outer_cacheability(u64 field) case GIC_BASER_CACHE_nC: return field; default: - return GIC_BASER_CACHE_nC; + return GIC_BASER_CACHE_SameAsInner; } } |