diff options
| author | Suresh Siddha <suresh.b.siddha@intel.com> | 2010-07-19 16:05:51 -0700 |
|---|---|---|
| committer | H. Peter Anvin <hpa@linux.intel.com> | 2010-07-19 16:48:06 -0700 |
| commit | 40e1d7a4ffee5cb17f5c36f4c3c4a011ab103ebe (patch) | |
| tree | 1009107780740bba57f789106007e461f333ae10 /arch | |
| parent | edb18f8ab02843453306601c4aa697f9691129cd (diff) | |
x86, cpu: Add xsaveopt cpufeature
Add cpu feature bit support for the XSAVEOPT instruction.
Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com>
LKML-Reference: <20100719230205.523204988@sbs-t61.sc.intel.com>
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/x86/include/asm/cpufeature.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h index 3ec9275cea46..d5ea3e3a8a42 100644 --- a/arch/x86/include/asm/cpufeature.h +++ b/arch/x86/include/asm/cpufeature.h @@ -165,6 +165,7 @@ #define X86_FEATURE_ARAT (7*32+ 1) /* Always Running APIC Timer */ #define X86_FEATURE_CPB (7*32+ 2) /* AMD Core Performance Boost */ #define X86_FEATURE_EPB (7*32+ 3) /* IA32_ENERGY_PERF_BIAS support */ +#define X86_FEATURE_XSAVEOPT (7*32+4) /* "xsaveopt" Optimized Xsave */ /* Virtualization flags: Linux defined, word 8 */ #define X86_FEATURE_TPR_SHADOW (8*32+ 0) /* Intel TPR Shadow */ |