diff options
| author | Colin Ian King <colin.king@canonical.com> | 2021-04-20 15:29:07 +0100 |
|---|---|---|
| committer | Peter Zijlstra <peterz@infradead.org> | 2021-04-23 09:03:15 +0200 |
| commit | 32d35c4a96ec79446f0d7be308a6eb248b507a0b (patch) | |
| tree | dc4f860f1d72b99aa639e93676ae258a15b44d30 /arch | |
| parent | 6a5f4386798d81f7f413e93c87e2b6de7439beea (diff) | |
perf/x86: Allow for 8<num_fixed_counters<16
The 64 bit value read from MSR_ARCH_PERFMON_FIXED_CTR_CTRL is being
bit-wise masked with the value (0x03 << i*4). However, the shifted value
is evaluated using 32 bit arithmetic, so will UB when i > 8. Fix this
by making 0x03 a ULL so that the shift is performed using 64 bit
arithmetic.
This makes the arithmetic internally consistent and preparers for the
day when hardware provides 8<num_fixed_counters<16.
Signed-off-by: Colin Ian King <colin.king@canonical.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/20210420142907.382417-1-colin.king@canonical.com
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/x86/events/core.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c index 3fe66b7aa721..c7fcc8d79f01 100644 --- a/arch/x86/events/core.c +++ b/arch/x86/events/core.c @@ -278,7 +278,7 @@ bool check_hw_exists(struct pmu *pmu, int num_counters, int num_counters_fixed) for (i = 0; i < num_counters_fixed; i++) { if (fixed_counter_disabled(i, pmu)) continue; - if (val & (0x03 << i*4)) { + if (val & (0x03ULL << i*4)) { bios_fail = 1; val_fail = val; reg_fail = reg; |