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authorChandrakala Chavva <cchavva@caviumnetworks.com>2015-01-15 16:11:08 +0300
committerRalf Baechle <ralf@linux-mips.org>2015-02-20 15:29:36 +0100
commit2d98cae6e35cfda8c008dba9c43c6f78f85e2792 (patch)
tree6e70675d29a49b129722a426b7fad04d05a0213c /arch
parent6b3a287e6351b00df6624b41c160e1c0817f40e2 (diff)
MIPS: OCTEON: Use correct instruction to read 64-bit COP0 register
Use dmfc0/dmtc0 instructions for reading CvmMemCtl COP0 register, its a 64-bit wide. Signed-off-by: Chandrakala Chavva <cchavva@caviumnetworks.com> Signed-off-by: Aleksey Makarov <aleksey.makarov@auriga.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: David Daney <david.daney@cavium.com> Patchwork: https://patchwork.linux-mips.org/patch/8936/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/mips/kernel/octeon_switch.S6
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/mips/kernel/octeon_switch.S b/arch/mips/kernel/octeon_switch.S
index 590ca2d56b6a..f0a699d73627 100644
--- a/arch/mips/kernel/octeon_switch.S
+++ b/arch/mips/kernel/octeon_switch.S
@@ -80,7 +80,7 @@
1:
#if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
/* Check if we need to store CVMSEG state */
- mfc0 t0, $11,7 /* CvmMemCtl */
+ dmfc0 t0, $11,7 /* CvmMemCtl */
bbit0 t0, 6, 3f /* Is user access enabled? */
/* Store the CVMSEG state */
@@ -104,9 +104,9 @@
.set reorder
/* Disable access to CVMSEG */
- mfc0 t0, $11,7 /* CvmMemCtl */
+ dmfc0 t0, $11,7 /* CvmMemCtl */
xori t0, t0, 0x40 /* Bit 6 is CVMSEG user enable */
- mtc0 t0, $11,7 /* CvmMemCtl */
+ dmtc0 t0, $11,7 /* CvmMemCtl */
#endif
3: