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| author | Stephane Eranian <eranian@google.com> | 2014-08-11 21:27:12 +0200 |
|---|---|---|
| committer | Ingo Molnar <mingo@kernel.org> | 2014-08-13 07:51:15 +0200 |
| commit | 770eee1fd38c70a009b321f5dbe64358f42511fd (patch) | |
| tree | 6d8f605feca5cff7e73edc4770545a48901d48ac /arch/x86/kernel/cpu/perf_event_amd_ibs.c | |
| parent | f3908b8cfb65ab6e78ac84df3b864eb22d5b6d9e (diff) | |
perf/x86: Fix data source encoding issues for load latency/precise store
This patch fixes issues introuduce by Andi's previous patch 'Revamp PEBS'
series.
This patch fixes the following:
- precise_store_data_hsw() encode the mem op type whenever we can
- precise_store_data_hsw set the default data source correctly
- 0 is not a valid init value for data source. Define PERF_MEM_NA as the
default value
This bug was actually introduced by
commit 722e76e60f2775c21b087ff12c5e678cf0ebcaaf
Author: Stephane Eranian <eranian@google.com>
Date: Thu May 15 17:56:44 2014 +0200
fix Haswell precise store data source encoding
Signed-off-by: Stephane Eranian <eranian@google.com>
Signed-off-by: Peter Zijlstra <peterz@infradead.org>
Link: http://lkml.kernel.org/r/1407785233-32193-4-git-send-email-eranian@google.com
Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
Cc: ak@linux.intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Diffstat (limited to 'arch/x86/kernel/cpu/perf_event_amd_ibs.c')
0 files changed, 0 insertions, 0 deletions