diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2014-01-20 12:06:50 -0800 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2014-01-20 12:06:50 -0800 |
commit | 4500cf60dbe4b7f514d11b24c3e1edfda2a6d69d (patch) | |
tree | 505dbd29e94178c8ae5b54c57f4bd81b0ee459fa /arch/x86/include | |
parent | 972d5e7e5b66f5a143026fcdd4b2be2f519c0f12 (diff) | |
parent | ee87c751d88f9b03fee7349556817fe80c113b32 (diff) |
Merge branch 'x86-intel-mid-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull Intel MID updates from Ingo Molnar:
"This tree improves Intel MID (Mobile Internet Device) platform
support:
- Merrifield platform support (David Cohen)
- Clovertrail platform support (Kuppuswamy Sathyanarayanan)
- Various cleanups and fixes (David Cohen)"
* 'x86-intel-mid-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
x86, intel_mid: Replace memcpy with struct assignment
x86, intel-mid: Return proper error code from get_gpio_by_name()
x86, intel-mid: Check get_gpio_by_name() error code on platform code
x86, intel-mid: sfi_handle_*_dev() should check for pdata error code
x86, intel-mid: Remove deprecated X86_MDFLD and X86_WANT_INTEL_MID configs
x86, intel-mid: Add Merrifield platform support
x86, intel-mid: Add Clovertrail platform support
x86, intel-mid: Move Medfield code out of intel-mid.c core file
Diffstat (limited to 'arch/x86/include')
-rw-r--r-- | arch/x86/include/asm/intel-mid.h | 48 |
1 files changed, 46 insertions, 2 deletions
diff --git a/arch/x86/include/asm/intel-mid.h b/arch/x86/include/asm/intel-mid.h index 459769d39263..e34e097b6f9d 100644 --- a/arch/x86/include/asm/intel-mid.h +++ b/arch/x86/include/asm/intel-mid.h @@ -51,10 +51,41 @@ struct devs_id { enum intel_mid_cpu_type { /* 1 was Moorestown */ INTEL_MID_CPU_CHIP_PENWELL = 2, + INTEL_MID_CPU_CHIP_CLOVERVIEW, + INTEL_MID_CPU_CHIP_TANGIER, }; extern enum intel_mid_cpu_type __intel_mid_cpu_chip; +/** + * struct intel_mid_ops - Interface between intel-mid & sub archs + * @arch_setup: arch_setup function to re-initialize platform + * structures (x86_init, x86_platform_init) + * + * This structure can be extended if any new interface is required + * between intel-mid & its sub arch files. + */ +struct intel_mid_ops { + void (*arch_setup)(void); +}; + +/* Helper API's for INTEL_MID_OPS_INIT */ +#define DECLARE_INTEL_MID_OPS_INIT(cpuname, cpuid) \ + [cpuid] = get_##cpuname##_ops + +/* Maximum number of CPU ops */ +#define MAX_CPU_OPS(a) (sizeof(a)/sizeof(void *)) + +/* + * For every new cpu addition, a weak get_<cpuname>_ops() function needs be + * declared in arch/x86/platform/intel_mid/intel_mid_weak_decls.h. + */ +#define INTEL_MID_OPS_INIT {\ + DECLARE_INTEL_MID_OPS_INIT(penwell, INTEL_MID_CPU_CHIP_PENWELL), \ + DECLARE_INTEL_MID_OPS_INIT(cloverview, INTEL_MID_CPU_CHIP_CLOVERVIEW), \ + DECLARE_INTEL_MID_OPS_INIT(tangier, INTEL_MID_CPU_CHIP_TANGIER) \ +}; + #ifdef CONFIG_X86_INTEL_MID static inline enum intel_mid_cpu_type intel_mid_identify_cpu(void) @@ -86,8 +117,21 @@ extern enum intel_mid_timer_options intel_mid_timer_options; * Penwell uses spread spectrum clock, so the freq number is not exactly * the same as reported by MSR based on SDM. */ -#define PENWELL_FSB_FREQ_83SKU 83200 -#define PENWELL_FSB_FREQ_100SKU 99840 +#define FSB_FREQ_83SKU 83200 +#define FSB_FREQ_100SKU 99840 +#define FSB_FREQ_133SKU 133000 + +#define FSB_FREQ_167SKU 167000 +#define FSB_FREQ_200SKU 200000 +#define FSB_FREQ_267SKU 267000 +#define FSB_FREQ_333SKU 333000 +#define FSB_FREQ_400SKU 400000 + +/* Bus Select SoC Fuse value */ +#define BSEL_SOC_FUSE_MASK 0x7 +#define BSEL_SOC_FUSE_001 0x1 /* FSB 133MHz */ +#define BSEL_SOC_FUSE_101 0x5 /* FSB 100MHz */ +#define BSEL_SOC_FUSE_111 0x7 /* FSB 83MHz */ #define SFI_MTMR_MAX_NUM 8 #define SFI_MRTC_MAX 8 |