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| author | Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> | 2016-03-01 09:45:13 +0530 |
|---|---|---|
| committer | Michael Ellerman <mpe@ellerman.id.au> | 2016-03-03 21:18:28 +1100 |
| commit | 368ced78e6ed3d72c2acc61233b58487071ec289 (patch) | |
| tree | 9660d69ec035efb99e5d5de7afffd36f0b1fad57 /arch/x86/crypto/sha256-avx-asm.S | |
| parent | ae9a71afa4d7cf29a816fbc387bfd59ad7c292b6 (diff) | |
powerpc/mm: Switch book3s 64 with 64K page size to 4 level page table
This is needed so that we can support both hash and radix page table
using single kernel. Radix kernel uses a 4 level table.
We now use physical address in upper page table tree levels. Even though
they are aligned to their size, for the masked bits we use the
bit positions as per PowerISA 3.0.
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Diffstat (limited to 'arch/x86/crypto/sha256-avx-asm.S')
0 files changed, 0 insertions, 0 deletions