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authorDavid S. Miller <davem@davemloft.net>2009-09-10 07:09:06 -0700
committerDavid S. Miller <davem@davemloft.net>2009-09-10 07:09:06 -0700
commit91b9286d819b821fd742c0053fe0748818374198 (patch)
tree681f74f971241a06a3db0e0604a99a938469dadd /arch/sparc
parent59abbd1e7cfd6018fb8e58a96aa562aaff8711e7 (diff)
sparc64: Provide hypervisor tracing bit support for perf counters.
A PMU need only specify which bit in the PCR enabled hypervisor tracing in order to enable this. This will be used in Niagara-2 perf counter support. Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'arch/sparc')
-rw-r--r--arch/sparc/kernel/perf_counter.c5
1 files changed, 4 insertions, 1 deletions
diff --git a/arch/sparc/kernel/perf_counter.c b/arch/sparc/kernel/perf_counter.c
index f2c781450d08..d86009fa6f8d 100644
--- a/arch/sparc/kernel/perf_counter.c
+++ b/arch/sparc/kernel/perf_counter.c
@@ -77,6 +77,7 @@ struct sparc_pmu {
int upper_shift;
int lower_shift;
int event_mask;
+ int hv_bit;
};
static const struct perf_event_map ultra3i_perfmon_event_map[] = {
@@ -178,7 +179,7 @@ void hw_perf_disable(void)
cpuc->enabled = 0;
val = pcr_ops->read();
- val &= ~(PCR_UTRACE | PCR_STRACE);
+ val &= ~(PCR_UTRACE | PCR_STRACE | sparc_pmu->hv_bit);
pcr_ops->write(val);
}
@@ -377,6 +378,8 @@ static int __hw_perf_counter_init(struct perf_counter *counter)
hwc->config_base |= PCR_UTRACE;
if (!attr->exclude_kernel)
hwc->config_base |= PCR_STRACE;
+ if (!attr->exclude_hv)
+ hwc->config_base |= sparc_pmu->hv_bit;
if (!hwc->sample_period) {
hwc->sample_period = MAX_PERIOD;