diff options
| author | Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | 2017-12-04 16:09:03 +0100 |
|---|---|---|
| committer | Rich Felker <dalias@libc.org> | 2018-04-12 19:47:55 -0400 |
| commit | 7dd7f69809b4e3bed5c28dd8600a3a8b20f6441c (patch) | |
| tree | 4a63a4e067b10bb9cfc1eff75176b8932c9f95b0 /arch/sh | |
| parent | 3aeb93a014058eb889cbb12c1f61f59666b9a081 (diff) | |
arch/sh: pcie-sh7786: mark unavailable PCI resource as disabled
Some PCI MEM resources are marked as IORESOURCE_MEM_32BIT, which means
they are only usable when the SH core runs in 32-bit mode. In 29-bit
mode, such memory regions are not usable.
The existing code for SH7786 properly skips such regions when
configuring the PCIe controller registers. However, because such
regions are still described in the resource array, the
pcibios_scanbus() function in the SuperH pci.c will register them to
the PCI core. Due to this, the PCI core will allocate MEM areas from
this resource, and assign BARs pointing to this area, even though it's
unusable.
In order to prevent this from happening, we mark such regions as
IORESOURCE_DISABLED, which tells the SuperH pci.c pcibios_scanbus()
function to skip them.
Note that we separate marking the region as disabled from skipping it,
because other regions will be marked as disabled in follow-up patches.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Rich Felker <dalias@libc.org>
Diffstat (limited to 'arch/sh')
| -rw-r--r-- | arch/sh/drivers/pci/pcie-sh7786.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/sh/drivers/pci/pcie-sh7786.c b/arch/sh/drivers/pci/pcie-sh7786.c index 0167a7352719..e713c398a6b9 100644 --- a/arch/sh/drivers/pci/pcie-sh7786.c +++ b/arch/sh/drivers/pci/pcie-sh7786.c @@ -438,6 +438,9 @@ static int __init pcie_init(struct sh7786_pcie_port *port) * mode, so just skip them entirely. */ if ((res->flags & IORESOURCE_MEM_32BIT) && __in_29bit_mode()) + res->flags |= IORESOURCE_DISABLED; + + if (res->flags & IORESOURCE_DISABLED) continue; pci_write_reg(chan, 0x00000000, SH4A_PCIEPTCTLR(win)); |