diff options
| author | Paul Mundt <lethal@linux-sh.org> | 2007-03-08 18:12:17 +0900 |
|---|---|---|
| committer | Paul Mundt <lethal@hera.kernel.org> | 2007-05-07 02:10:51 +0000 |
| commit | 45ed285b54930767937deb0eaf718b1d08c3c475 (patch) | |
| tree | 6132a0116f3c6370884d64928dbc2825b964f510 /arch/sh | |
| parent | fc31b80957a14a60513d953cc67a55519a2b09c7 (diff) | |
sh: speculative execution support for SH7780.
SH7780 has a speculative execution mode where it can speculatively
perform an instruction fetch for subroutine returns, this allows it
to be enabled. There are some various pitfalls associated with this
mode, so it's left as depending on CONFIG_EXPERIMENTAL and not
enabled by default.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh')
| -rw-r--r-- | arch/sh/Kconfig | 10 | ||||
| -rw-r--r-- | arch/sh/kernel/cpu/init.c | 19 |
2 files changed, 29 insertions, 0 deletions
diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig index 4d16d8917074..2715834f72be 100644 --- a/arch/sh/Kconfig +++ b/arch/sh/Kconfig @@ -366,6 +366,16 @@ config SH_STORE_QUEUES Selecting this option will enable an in-kernel API for manipulating the store queues integrated in the SH-4 processors. +config SPECULATIVE_EXECUTION + bool "Speculative subroutine return" + depends on CPU_SUBTYPE_SH7780 && EXPERIMENTAL + help + This enables support for a speculative instruction fetch for + subroutine return. There are various pitfalls associated with + this, as outlined in the SH7780 hardware manual. + + If unsure, say N. + config CPU_HAS_INTEVT bool diff --git a/arch/sh/kernel/cpu/init.c b/arch/sh/kernel/cpu/init.c index 726acfcb9b77..6451ad630174 100644 --- a/arch/sh/kernel/cpu/init.c +++ b/arch/sh/kernel/cpu/init.c @@ -41,6 +41,23 @@ __setup("no" __stringify(x), x##_setup); onchip_setup(fpu); onchip_setup(dsp); +#ifdef CONFIG_SPECULATIVE_EXECUTION +#define CPUOPM 0xff2f0000 +#define CPUOPM_RABD (1 << 5) + +static void __init speculative_execution_init(void) +{ + /* Clear RABD */ + ctrl_outl(ctrl_inl(CPUOPM) & ~CPUOPM_RABD, CPUOPM); + + /* Flush the update */ + (void)ctrl_inl(CPUOPM); + ctrl_barrier(); +} +#else +#define speculative_execution_init() do { } while (0) +#endif + /* * Generic first-level cache init */ @@ -261,4 +278,6 @@ asmlinkage void __init sh_cpu_init(void) */ ubc_wakeup(); #endif + + speculative_execution_init(); } |