diff options
| author | Paul Mundt <lethal@linux-sh.org> | 2007-05-08 15:31:48 +0900 |
|---|---|---|
| committer | Paul Mundt <lethal@hera.kernel.org> | 2007-05-09 01:35:01 +0000 |
| commit | 53f983a90d7908bcece51f86180c7c9b575a1e4d (patch) | |
| tree | da5914e6f18e8dd55563697de7339af2d99d9c18 /arch/sh/kernel/traps.c | |
| parent | bd0799977cb9b68aa6a39e9630aeea4778a58385 (diff) | |
sh: Fix PC adjustments for varying opcode length.
There are a few different cases for figuring out how to
size the instruction. We read in the instruction located
at regs->pc - 4 when rewinding the opcode to figure out if
there's a 32-bit opcode before the faulting instruction, with
a default of a - 2 adjustment on a mismatch. In practice this
works for the cases where pc - 4 is just another 16-bit opcode,
or we happen to have a 32-bit and a 16-bit immediately
preceeding the pc value.
In the cases where we aren't rewinding, this is much less ugly..
We also don't bother fixing up the places where we're explicitly
dealing with 16-bit instructions, since this might lead to
confusion regarding the encoding size possibilities on other
CPU variants.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/kernel/traps.c')
| -rw-r--r-- | arch/sh/kernel/traps.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/sh/kernel/traps.c b/arch/sh/kernel/traps.c index 7b40f0ff3dfc..1446d12ba220 100644 --- a/arch/sh/kernel/traps.c +++ b/arch/sh/kernel/traps.c @@ -505,7 +505,7 @@ static int handle_unaligned_access(u16 instruction, struct pt_regs *regs) simple: ret = handle_unaligned_ins(instruction,regs); if (ret==0) - regs->pc += 2; + regs->pc += instruction_size(instruction); return ret; } #endif /* CONFIG_CPU_SH2A */ @@ -682,7 +682,7 @@ asmlinkage void do_reserved_inst(unsigned long r4, unsigned long r5, err = do_fpu_inst(inst, regs); if (!err) { - regs->pc += 2; + regs->pc += instruction_size(inst); return; } /* not a FPU inst. */ |