sh: MS7712SE01 board support.

Support the SH7712 (SH3-DSP) Solution Engine reference board.

Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>

3 files changed, 64 insertions, 0 deletions

diff --git a/arch/sh/kernel/cpu/sh3/Makefile b/arch/sh/kernel/cpu/sh3/Makefile
index 83905e4e4387..09faa056cd43 100644
--- a/arch/sh/kernel/cpu/sh3/Makefile
+++ b/arch/sh/kernel/cpu/sh3/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_CPU_SUBTYPE_SH7708)	+= setup-sh7708.o
 obj-$(CONFIG_CPU_SUBTYPE_SH7709)	+= setup-sh7709.o
 obj-$(CONFIG_CPU_SUBTYPE_SH7300)	+= setup-sh7300.o
 obj-$(CONFIG_CPU_SUBTYPE_SH7710)	+= setup-sh7710.o
+obj-$(CONFIG_CPU_SUBTYPE_SH7712)	+= setup-sh7710.o
 
 # Primary on-chip clocks (common)
 clock-$(CONFIG_CPU_SH3)			:= clock-sh3.o
diff --git a/arch/sh/kernel/cpu/sh3/probe.c b/arch/sh/kernel/cpu/sh3/probe.c
index 821b0ab7b528..647623b22edc 100644
--- a/arch/sh/kernel/cpu/sh3/probe.c
+++ b/arch/sh/kernel/cpu/sh3/probe.c
@@ -78,6 +78,9 @@ int __init detect_cpu_and_cache_system(void)
 #if defined(CONFIG_CPU_SUBTYPE_SH7710)
 		current_cpu_data.type = CPU_SH7710;
 #endif
+#if defined(CONFIG_CPU_SUBTYPE_SH7712)
+		current_cpu_data.type = CPU_SH7712;
+#endif
 #if defined(CONFIG_CPU_SUBTYPE_SH7705)
 		current_cpu_data.type = CPU_SH7705;
 
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7710.c b/arch/sh/kernel/cpu/sh3/setup-sh7710.c
index 895f99ee6a95..51760a7e7f1c 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh7710.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh7710.c
@@ -2,6 +2,7 @@
  * SH7710 Setup
  *
  *  Copyright (C) 2006  Paul Mundt
+ *  Copyright (C) 2007  Nobuhiro Iwamatsu
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
@@ -19,6 +20,12 @@ static struct plat_sci_port sci_platform_data[] = {
 		.type		= PORT_SCIF,
 		.irqs		= { 52, 53, 55, 54 },
 	}, {
+		.mapbase	= 0xa4420000,
+		.flags		= UPF_BOOT_AUTOCONF,
+		.type		= PORT_SCIF,
+		.irqs           = { 56, 57, 59, 58 },
+	}, {
+
 		.flags = 0,
 	}
 };
@@ -41,3 +48,56 @@ static int __init sh7710_devices_setup(void)
 				    ARRAY_SIZE(sh7710_devices));
 }
 __initcall(sh7710_devices_setup);
+
+static struct ipr_data sh7710_ipr_map[] = {
+	/* IRQ, IPR-idx, shift, priority */
+	{ 16, 0, 12, 2 }, /* TMU0 TUNI*/
+	{ 17, 0,  8, 2 }, /* TMU1 TUNI */
+	{ 18, 0,  4, 2 }, /* TMU2 TUNI */
+	{ 27, 1, 12, 2 }, /* WDT ITI */
+	{ 20, 0,  0, 2 }, /* RTC ATI (alarm) */
+	{ 21, 0,  0, 2 }, /* RTC PRI (period) */
+	{ 22, 0,  0, 2 }, /* RTC CUI (carry) */
+	{ 48, 4, 12, 7 }, /* DMAC DMTE0 */
+	{ 49, 4, 12, 7 }, /* DMAC DMTE1 */
+	{ 50, 4, 12, 7 }, /* DMAC DMTE2 */
+	{ 51, 4, 12, 7 }, /* DMAC DMTE3 */
+	{ 52, 4,  8, 3 }, /* SCIF0 ERI */
+	{ 53, 4,  8, 3 }, /* SCIF0 RXI */
+	{ 54, 4,  8, 3 }, /* SCIF0 BRI */
+	{ 55, 4,  8, 3 }, /* SCIF0 TXI */
+	{ 56, 4,  4, 3 }, /* SCIF1 ERI */
+	{ 57, 4,  4, 3 }, /* SCIF1 RXI */
+	{ 58, 4,  4, 3 }, /* SCIF1 BRI */
+	{ 59, 4,  4, 3 }, /* SCIF1 TXI */
+	{ 76, 5,  8, 7 }, /* DMAC DMTE4 */
+	{ 77, 5,  8, 7 }, /* DMAC DMTE5 */
+	{ 80, 6, 12, 5 }, /* EDMAC EINT0 */
+	{ 81, 6,  8, 5 }, /* EDMAC EINT1 */
+	{ 82, 6,  4, 5 }, /* EDMAC EINT2 */
+};
+
+static unsigned long ipr_offsets[] = {
+	0xA414FEE2	/* 0: IPRA */
+,	0xA414FEE4	/* 1: IPRB */
+,	0xA4140016	/* 2: IPRC */
+,	0xA4140018	/* 3: IPRD */
+,	0xA414001A	/* 4: IPRE */
+,	0xA4080000	/* 5: IPRF */
+,	0xA4080002	/* 6: IPRG */
+,	0xA4080004	/* 7: IPRH */
+,	0xA4080006	/* 8: IPRI */
+};
+
+/* given the IPR index return the address of the IPR register */
+unsigned int map_ipridx_to_addr(int idx)
+{
+	if (idx >= ARRAY_SIZE(ipr_offsets))
+		return 0;
+	return ipr_offsets[idx];
+}
+
+void __init init_IRQ_ipr()
+{
+	make_ipr_irq(sh7710_ipr_map, ARRAY_SIZE(sh7710_ipr_map));
+}