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author | Palmer Dabbelt <palmer@dabbelt.com> | 2017-07-10 18:02:19 -0700 |
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committer | Palmer Dabbelt <palmer@dabbelt.com> | 2017-09-26 15:26:45 -0700 |
commit | fab957c11efe2f405e08b9f0d080524bc2631428 (patch) | |
tree | f42fd6aca01844c410583cbad08c83a75b387ebf /arch/riscv/lib | |
parent | 76d2a0493a17d4c8ecc781366850c3c4f8e1a446 (diff) |
RISC-V: Atomic and Locking Code
This contains all the code that directly interfaces with the RISC-V
memory model. While this code corforms to the current RISC-V ISA
specifications (user 2.2 and priv 1.10), the memory model is somewhat
underspecified in those documents. There is a working group that hopes
to produce a formal memory model by the end of the year, but my
understanding is that the basic definitions we're relying on here won't
change significantly.
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com>
Diffstat (limited to 'arch/riscv/lib')
0 files changed, 0 insertions, 0 deletions