diff options
| author | Baruch Siach <baruch@tkos.co.il> | 2020-04-21 12:04:46 +0300 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2020-04-23 12:31:41 -0700 |
| commit | 829e7573c45a97e0f6a923a8e6e4589c26a26df2 (patch) | |
| tree | 592076f138c52294d7cb589dd2cff152dad1fe9a /arch/powerpc | |
| parent | 7c74b0bec918c1e0ca0b4208038c156eacf8f13f (diff) | |
net: phy: marvell10g: limit soft reset to 88x3310
The MV_V2_PORT_CTRL_SWRST bit in MV_V2_PORT_CTRL is reserved on 88E2110.
Setting SWRST on 88E2110 breaks packets transfer after interface down/up
cycle.
Fixes: 8f48c2ac85ed ("net: marvell10g: soft-reset the PHY when coming out of low power")
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'arch/powerpc')
0 files changed, 0 insertions, 0 deletions