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authorVarun Sethi <Varun.Sethi@freescale.com>2012-04-25 01:27:34 +0000
committerAlexander Graf <agraf@suse.de>2012-05-06 16:19:09 +0200
commit30124906db8598255fba32c8bf0adb7e8f1503ab (patch)
tree5a59fb02e1129c5614ec608739dd1a758db5a091 /arch/powerpc/kvm/bookehv_interrupts.S
parent3d4c6826ed2a28e69e8ee14f1d58c4c8622f04b3 (diff)
KVM: PPC: booke(hv): Fix save/restore of guest accessible SPRGs.
For Guest accessible SPRGs 4-7, save/restore must be handled differently for 64bit and non-64 bit case. Use the PPC_STD/PPC_LD macros for saving/restoring to/from these registers. Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'arch/powerpc/kvm/bookehv_interrupts.S')
-rw-r--r--arch/powerpc/kvm/bookehv_interrupts.S16
1 files changed, 8 insertions, 8 deletions
diff --git a/arch/powerpc/kvm/bookehv_interrupts.S b/arch/powerpc/kvm/bookehv_interrupts.S
index 41d34850f826..b7608ac52b66 100644
--- a/arch/powerpc/kvm/bookehv_interrupts.S
+++ b/arch/powerpc/kvm/bookehv_interrupts.S
@@ -316,13 +316,13 @@ _GLOBAL(kvmppc_resume_host)
PPC_STL r5, VCPU_LR(r4)
mfspr r7, SPRN_SPRG5
PPC_STL r3, VCPU_VRSAVE(r4)
- PPC_STL r6, VCPU_SHARED_SPRG4(r11)
+ PPC_STD(r6, VCPU_SHARED_SPRG4, r11)
mfspr r8, SPRN_SPRG6
- PPC_STL r7, VCPU_SHARED_SPRG5(r11)
+ PPC_STD(r7, VCPU_SHARED_SPRG5, r11)
mfspr r9, SPRN_SPRG7
- PPC_STL r8, VCPU_SHARED_SPRG6(r11)
+ PPC_STD(r8, VCPU_SHARED_SPRG6, r11)
mfxer r3
- PPC_STL r9, VCPU_SHARED_SPRG7(r11)
+ PPC_STD(r9, VCPU_SHARED_SPRG7, r11)
/* save guest MAS registers and restore host mas4 & mas6 */
mfspr r5, SPRN_MAS0
@@ -537,13 +537,13 @@ lightweight_exit:
* SPRGs, so we need to reload them here with the guest's values.
*/
lwz r3, VCPU_VRSAVE(r4)
- lwz r5, VCPU_SHARED_SPRG4(r11)
+ PPC_LD(r5, VCPU_SHARED_SPRG4, r11)
mtspr SPRN_VRSAVE, r3
- lwz r6, VCPU_SHARED_SPRG5(r11)
+ PPC_LD(r6, VCPU_SHARED_SPRG5, r11)
mtspr SPRN_SPRG4W, r5
- lwz r7, VCPU_SHARED_SPRG6(r11)
+ PPC_LD(r7, VCPU_SHARED_SPRG6, r11)
mtspr SPRN_SPRG5W, r6
- lwz r8, VCPU_SHARED_SPRG7(r11)
+ PPC_LD(r8, VCPU_SHARED_SPRG7, r11)
mtspr SPRN_SPRG6W, r7
mtspr SPRN_SPRG7W, r8