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| author | Alexander Graf <agraf@suse.de> | 2014-04-25 16:07:21 +0200 |
|---|---|---|
| committer | Alexander Graf <agraf@suse.de> | 2014-05-30 14:26:22 +0200 |
| commit | a5948fa092a04dfd6b9ee31c99eb6896c158eb08 (patch) | |
| tree | 228059928f720af84ba0a9211eee2bf557e238ee /arch/powerpc/kvm/book3s_emulate.c | |
| parent | f8f6eb0d189cf2724af5ebc8cad460c78fb1994e (diff) | |
KVM: PPC: Book3S PR: Emulate TIR register
In parallel to the Processor ID Register (PIR) threaded POWER8 also adds a
Thread ID Register (TIR). Since PR KVM doesn't emulate more than one thread
per core, we can just always expose 0 here.
Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'arch/powerpc/kvm/book3s_emulate.c')
| -rw-r--r-- | arch/powerpc/kvm/book3s_emulate.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/powerpc/kvm/book3s_emulate.c b/arch/powerpc/kvm/book3s_emulate.c index 52448ef499cb..0a1de29a4caf 100644 --- a/arch/powerpc/kvm/book3s_emulate.c +++ b/arch/powerpc/kvm/book3s_emulate.c @@ -566,6 +566,7 @@ int kvmppc_core_emulate_mfspr_pr(struct kvm_vcpu *vcpu, int sprn, ulong *spr_val case SPRN_MMCR0: case SPRN_MMCR1: case SPRN_MMCR2: + case SPRN_TIR: #endif *spr_val = 0; break; |