diff options
| author | LEROY Christophe <christophe.leroy@c-s.fr> | 2014-08-29 11:14:37 +0200 |
|---|---|---|
| committer | Scott Wood <scottwood@freescale.com> | 2014-09-04 19:13:31 -0500 |
| commit | 3e43640346507caaa0b3b03882a93f641ace4e58 (patch) | |
| tree | d90346180bc106c0d888d539456327d028bc8734 /arch/powerpc/kernel | |
| parent | 92625d491e59719f5241bad31eb0f2295479b019 (diff) | |
powerpc/8xx: Remove loading of r10 at end of FixupDAR
Since commit 2321f33790a6c5b80322d907a92d5739e7521a13, r10 is not used anymore
after FixupDAR. There is therefore no need to set it up with the value of DAR.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Diffstat (limited to 'arch/powerpc/kernel')
| -rw-r--r-- | arch/powerpc/kernel/head_8xx.S | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S index 17158089833b..0bed748bbb85 100644 --- a/arch/powerpc/kernel/head_8xx.S +++ b/arch/powerpc/kernel/head_8xx.S @@ -498,7 +498,7 @@ DataTLBError: mfspr r10, SPRN_DAR cmpwi cr0, r10, 0x00f0 beq- FixupDAR /* must be a buggy dcbX, icbi insn. */ -DARFixed:/* Return from dcbx instruction bug workaround, r10 holds value of DAR */ +DARFixed:/* Return from dcbx instruction bug workaround */ #ifdef CONFIG_8xx_CPU6 lwz r3, 8(r0) #endif @@ -527,7 +527,7 @@ DARFixed:/* Return from dcbx instruction bug workaround, r10 holds value of DAR /* This is the procedure to calculate the data EA for buggy dcbx,dcbi instructions * by decoding the registers used by the dcbx instruction and adding them. - * DAR is set to the calculated address and r10 also holds the EA on exit. + * DAR is set to the calculated address. */ /* define if you don't want to use self modifying code */ #define NO_SELF_MODIFYING_CODE @@ -567,8 +567,7 @@ FixupDAR:/* Entry point for dcbx workaround. */ beq+ 142f cmpwi cr0, r10, 1964 /* Is icbi? */ beq+ 142f -141: mfspr r10, SPRN_DAR /* r10 must hold DAR at exit */ - b DARFixed /* Nope, go back to normal TLB processing */ +141: b DARFixed /* Nope, go back to normal TLB processing */ 144: mfspr r10, SPRN_DSISR rlwinm r10, r10,0,7,5 /* Clear store bit for buggy dcbst insn */ |