diff options
| author | Paul Mackerras <paulus@ozlabs.org> | 2017-08-30 16:34:09 +1000 |
|---|---|---|
| committer | Michael Ellerman <mpe@ellerman.id.au> | 2017-09-01 16:42:44 +1000 |
| commit | d2b65ac6526a82965212b632d42687251e122a36 (patch) | |
| tree | f9992c13e7d20b5ccff321973d9e7cdc57392332 /arch/powerpc/include | |
| parent | 31bfdb036f1281831db2532178f0da41f4dc9bed (diff) | |
powerpc: Emulate load/store floating point as integer word instructions
This adds emulation for the lfiwax, lfiwzx and stfiwx instructions.
This necessitated adding a new flag to indicate whether a floating
point or an integer conversion was needed for LOAD_FP and STORE_FP,
so this moves the size field in op->type up 4 bits.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Diffstat (limited to 'arch/powerpc/include')
| -rw-r--r-- | arch/powerpc/include/asm/sstep.h | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/arch/powerpc/include/asm/sstep.h b/arch/powerpc/include/asm/sstep.h index 309d1c5de143..ab9d849644d0 100644 --- a/arch/powerpc/include/asm/sstep.h +++ b/arch/powerpc/include/asm/sstep.h @@ -68,6 +68,7 @@ enum instruction_type { #define SIGNEXT 0x20 #define UPDATE 0x40 /* matches bit in opcode 31 instructions */ #define BYTEREV 0x80 +#define FPCONV 0x100 /* Barrier type field, ORed in with type */ #define BARRIER_MASK 0xe0 @@ -93,8 +94,8 @@ enum instruction_type { #define VSX_CHECK_VEC 8 /* check MSR_VEC not MSR_VSX for reg >= 32 */ /* Size field in type word */ -#define SIZE(n) ((n) << 8) -#define GETSIZE(w) ((w) >> 8) +#define SIZE(n) ((n) << 12) +#define GETSIZE(w) ((w) >> 12) #define MKOP(t, f, s) ((t) | (f) | SIZE(s)) |