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| author | Michael Ellerman <mpe@ellerman.id.au> | 2020-05-20 23:38:13 +1000 |
|---|---|---|
| committer | Michael Ellerman <mpe@ellerman.id.au> | 2020-05-20 23:38:13 +1000 |
| commit | 787a2b682d18997e71efc2ae92ce158ca3e319e9 (patch) | |
| tree | 3687b6fa74d576bab27183aae7d8124517b7fbeb /arch/powerpc/include | |
| parent | 217ba7dccef8e811eee43003bfef24f1902f37c9 (diff) | |
| parent | b1f9be9392f090f08e4ad9e2c68963aeff03bd67 (diff) | |
Merge branch 'topic/ppc-kvm' into next
Merge our topic branch shared with the kvm-ppc tree.
This brings in one commit that touches the XIVE interrupt controller
logic across core and KVM code.
Diffstat (limited to 'arch/powerpc/include')
| -rw-r--r-- | arch/powerpc/include/asm/xive-regs.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/xive-regs.h b/arch/powerpc/include/asm/xive-regs.h index 33aee7490cbb..8b211faa0e42 100644 --- a/arch/powerpc/include/asm/xive-regs.h +++ b/arch/powerpc/include/asm/xive-regs.h @@ -37,6 +37,14 @@ #define XIVE_ESB_SET_PQ_10 0xe00 /* Load */ #define XIVE_ESB_SET_PQ_11 0xf00 /* Load */ +/* + * Load-after-store ordering + * + * Adding this offset to the load address will enforce + * load-after-store ordering. This is required to use StoreEOI. + */ +#define XIVE_ESB_LD_ST_MO 0x40 /* Load-after-store ordering */ + #define XIVE_ESB_VAL_P 0x2 #define XIVE_ESB_VAL_Q 0x1 #define XIVE_ESB_INVALID 0xFF |