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authorMike Dyer <mike.dyer@md-soft.co.uk>2013-08-16 18:36:28 +0100
committerMark Brown <broonie@linaro.org>2013-08-18 16:30:26 +0100
commit85fa532b6ef920b32598df86b194571a7059a77c (patch)
treea8e6b1f126b056005af744fc5d408458ed472f62 /arch/powerpc/configs/mpc512x_defconfig
parentd4e4ab86bcba5a72779c43dc1459f71fea3d89c8 (diff)
ASoC: wm8960: Fix PLL register writes
Bit 9 of PLL2,3 and 4 is reserved as '0'. The 24bit fractional part should be split across each register in 8bit chunks. Signed-off-by: Mike Dyer <mike.dyer@md-soft.co.uk> Signed-off-by: Mark Brown <broonie@linaro.org> Cc: stable@vger.kernel.org
Diffstat (limited to 'arch/powerpc/configs/mpc512x_defconfig')
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