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authorScott Wood <scottwood@freescale.com>2013-08-20 19:33:12 -0500
committerScott Wood <scottwood@freescale.com>2013-08-20 19:33:12 -0500
commitbeb2dc0a7a84be003ce54e98b95d65cc66e6e536 (patch)
treea30c97effb8f723cccbc343306df4c7b6ab0047b /arch/powerpc/boot
parentd52459ca3047435aa5d7957e50857fc7ba193411 (diff)
powerpc: Convert some mftb/mftbu into mfspr
Some CPUs (such as e500v1/v2) don't implement mftb and will take a trap. mfspr should work on everything that has a timebase, and is the preferred instruction according to ISA v2.06. Currently we get away with mftb on 85xx because the assembler converts it to mfspr due to -Wa,-me500. However, that flag has other effects that are undesireable for certain targets (e.g. lwsync is converted to sync), and is hostile to multiplatform kernels. Thus we would like to stop setting it for all e500-family builds. mftb/mftbu instances which are in 85xx code or common code are converted. Instances which will never run on 85xx are left alone. Signed-off-by: Scott Wood <scottwood@freescale.com>
Diffstat (limited to 'arch/powerpc/boot')
-rw-r--r--arch/powerpc/boot/ppc_asm.h3
-rw-r--r--arch/powerpc/boot/util.S10
2 files changed, 8 insertions, 5 deletions
diff --git a/arch/powerpc/boot/ppc_asm.h b/arch/powerpc/boot/ppc_asm.h
index 1c2c2817f9b7..eb0e98be69e0 100644
--- a/arch/powerpc/boot/ppc_asm.h
+++ b/arch/powerpc/boot/ppc_asm.h
@@ -59,4 +59,7 @@
#define r30 30
#define r31 31
+#define SPRN_TBRL 268
+#define SPRN_TBRU 269
+
#endif /* _PPC64_PPC_ASM_H */
diff --git a/arch/powerpc/boot/util.S b/arch/powerpc/boot/util.S
index 427ddfc11991..5143228e3e5f 100644
--- a/arch/powerpc/boot/util.S
+++ b/arch/powerpc/boot/util.S
@@ -71,18 +71,18 @@ udelay:
add r4,r4,r5
addi r4,r4,-1
divw r4,r4,r5 /* BUS ticks */
-1: mftbu r5
- mftb r6
- mftbu r7
+1: mfspr r5, SPRN_TBRU
+ mfspr r6, SPRN_TBRL
+ mfspr r7, SPRN_TBRU
cmpw 0,r5,r7
bne 1b /* Get [synced] base time */
addc r9,r6,r4 /* Compute end time */
addze r8,r5
-2: mftbu r5
+2: mfspr r5, SPRN_TBRU
cmpw 0,r5,r8
blt 2b
bgt 3f
- mftb r6
+ mfspr r6, SPRN_TBRL
cmpw 0,r6,r9
blt 2b
3: blr