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| author | Atish Patra <atish.patra@wdc.com> | 2018-10-02 12:14:58 -0700 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@sifive.com> | 2018-10-22 17:03:36 -0700 |
| commit | 6db170ff4c088caaf7806c00b29a55f6df07d7b6 (patch) | |
| tree | d91d87868100acbbf8436728ebcdccc152689766 /arch/openrisc/kernel/module.c | |
| parent | b18d6f05252d6b3f725c08d8831a46b003df5b6b (diff) | |
RISC-V: Disable preemption before enabling interrupts
Currently, irq is enabled before preemption disabling happens.
If the scheduler fired right here and cpu is scheduled then it
may blow up.
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
[Atish: Commit text and code comment formatting update]
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'arch/openrisc/kernel/module.c')
0 files changed, 0 insertions, 0 deletions