diff options
| author | David Howells <dhowells@redhat.com> | 2018-03-08 09:48:46 +0000 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2018-03-09 23:19:56 +0100 |
| commit | 739d875dd6982618020d30f58f8acf10f6076e6d (patch) | |
| tree | 13deb11d5b2078e49d4e5b6175e5846a22a04b95 /arch/mn10300/proc-mn2ws0050/include/proc/cache.h | |
| parent | b67aea2bbab780e412b8af3386cc9f78f61a4cac (diff) | |
mn10300: Remove the architecture
Remove the MN10300 arch as the hardware is defunct.
Suggested-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: David Howells <dhowells@redhat.com>
cc: Masahiro Yamada <yamada.masahiro@socionext.com>
cc: linux-am33-list@redhat.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/mn10300/proc-mn2ws0050/include/proc/cache.h')
| -rw-r--r-- | arch/mn10300/proc-mn2ws0050/include/proc/cache.h | 49 |
1 files changed, 0 insertions, 49 deletions
diff --git a/arch/mn10300/proc-mn2ws0050/include/proc/cache.h b/arch/mn10300/proc-mn2ws0050/include/proc/cache.h deleted file mode 100644 index bcb5df2d892f..000000000000 --- a/arch/mn10300/proc-mn2ws0050/include/proc/cache.h +++ /dev/null @@ -1,49 +0,0 @@ -/* Cache specification - * - * Copyright (C) 2005 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * Modified by Matsushita Electric Industrial Co., Ltd. - * Modifications: - * 13-Nov-2006 MEI Add L1_CACHE_SHIFT_MAX definition. - * 29-Jul-2008 MEI Add define for MN10300_HAS_AREAPURGE_REG. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ -#ifndef _ASM_PROC_CACHE_H -#define _ASM_PROC_CACHE_H - -/* - * L1 cache - */ -#define L1_CACHE_NWAYS 4 /* number of ways in caches */ -#define L1_CACHE_NENTRIES 128 /* number of entries in each way */ -#define L1_CACHE_BYTES 32 /* bytes per entry */ -#define L1_CACHE_SHIFT 5 /* shift for bytes per entry */ -#define L1_CACHE_WAYDISP 0x1000 /* distance from one way to the next */ - -#define L1_CACHE_TAG_VALID 0x00000001 /* cache tag valid bit */ -#define L1_CACHE_TAG_DIRTY 0x00000008 /* data cache tag dirty bit */ -#define L1_CACHE_TAG_ENTRY 0x00000fe0 /* cache tag entry address mask */ -#define L1_CACHE_TAG_ADDRESS 0xfffff000 /* cache tag line address mask */ -#define L1_CACHE_TAG_MASK +(L1_CACHE_TAG_ADDRESS|L1_CACHE_TAG_ENTRY) - -/* - * specification of the interval between interrupt checking intervals whilst - * managing the cache with the interrupts disabled - */ -#define MN10300_DCACHE_INV_RANGE_INTR_LOG2_INTERVAL 4 - -/* - * The size of range at which it becomes more economical to just flush the - * whole cache rather than trying to flush the specified range. - */ -#define MN10300_DCACHE_FLUSH_BORDER \ - +(L1_CACHE_NWAYS * L1_CACHE_NENTRIES * L1_CACHE_BYTES) -#define MN10300_DCACHE_FLUSH_INV_BORDER \ - +(L1_CACHE_NWAYS * L1_CACHE_NENTRIES * L1_CACHE_BYTES) - -#endif /* _ASM_PROC_CACHE_H */ |