diff options
| author | 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> | 2021-06-26 14:18:40 +0800 |
|---|---|---|
| committer | Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2021-06-30 14:37:16 +0200 |
| commit | 23c64447b3538a6f34cb38aae3bc19dc1ec53436 (patch) | |
| tree | 8a1c83e85af03c8d6be06c0b9b5db01352036daf /arch/mips | |
| parent | ab3040e1379bd6fcc260f1f7558ee9c2da62766b (diff) | |
MIPS: CI20: Reduce clocksource to 750 kHz.
The original clock (3 MHz) is too fast for the clocksource,
there will be a chance that the system may get stuck.
Reported-by: Nikolaus Schaller <hns@goldelico.com>
Tested-by: Nikolaus Schaller <hns@goldelico.com> # on CI20
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Acked-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Diffstat (limited to 'arch/mips')
| -rw-r--r-- | arch/mips/boot/dts/ingenic/ci20.dts | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/mips/boot/dts/ingenic/ci20.dts b/arch/mips/boot/dts/ingenic/ci20.dts index 8877c62609de..3a4eaf1f3f48 100644 --- a/arch/mips/boot/dts/ingenic/ci20.dts +++ b/arch/mips/boot/dts/ingenic/ci20.dts @@ -525,10 +525,10 @@ &tcu { /* - * 750 kHz for the system timer and 3 MHz for the clocksource, + * 750 kHz for the system timer and clocksource, * use channel #0 for the system timer, #1 for the clocksource. */ assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>, <&tcu TCU_CLK_OST>; - assigned-clock-rates = <750000>, <3000000>, <3000000>; + assigned-clock-rates = <750000>, <750000>, <3000000>; }; |