diff options
| author | Hauke Mehrtens <hauke@hauke-m.de> | 2013-12-22 14:36:32 +0100 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2014-01-22 20:18:56 +0100 |
| commit | 0ded1becc8deaea66f8837c274fd84facc257919 (patch) | |
| tree | 3d6977f598deda45e25dac0a2576abb86855118c /arch/mips | |
| parent | d775c966c0602d3ea2fad51594e995f2d798b919 (diff) | |
MIPS: BCM47XX: add vectored interrupt support
This adds support for vectored interrupt which is supported by the SoC
using a MIPS 74K CPU like the BCM4716 and BCM4706.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6290/
Diffstat (limited to 'arch/mips')
| -rw-r--r-- | arch/mips/bcm47xx/Kconfig | 1 | ||||
| -rw-r--r-- | arch/mips/bcm47xx/irq.c | 23 |
2 files changed, 24 insertions, 0 deletions
diff --git a/arch/mips/bcm47xx/Kconfig b/arch/mips/bcm47xx/Kconfig index a29f51dd373e..df549af380af 100644 --- a/arch/mips/bcm47xx/Kconfig +++ b/arch/mips/bcm47xx/Kconfig @@ -21,6 +21,7 @@ config BCM47XX_SSB config BCM47XX_BCMA bool "BCMA Support for Broadcom BCM47XX" select SYS_HAS_CPU_MIPS32_R2 + select CPU_MIPSR2_IRQ_VI select BCMA select BCMA_HOST_SOC select BCMA_DRIVER_MIPS diff --git a/arch/mips/bcm47xx/irq.c b/arch/mips/bcm47xx/irq.c index a9133e9757a0..e0585b76ec19 100644 --- a/arch/mips/bcm47xx/irq.c +++ b/arch/mips/bcm47xx/irq.c @@ -25,6 +25,7 @@ #include <linux/types.h> #include <linux/interrupt.h> #include <linux/irq.h> +#include <asm/setup.h> #include <asm/irq_cpu.h> #include <bcm47xx.h> @@ -50,6 +51,18 @@ asmlinkage void plat_irq_dispatch(void) do_IRQ(6); } +#define DEFINE_HWx_IRQDISPATCH(x) \ + static void bcm47xx_hw ## x ## _irqdispatch(void) \ + { \ + do_IRQ(x); \ + } +DEFINE_HWx_IRQDISPATCH(2) +DEFINE_HWx_IRQDISPATCH(3) +DEFINE_HWx_IRQDISPATCH(4) +DEFINE_HWx_IRQDISPATCH(5) +DEFINE_HWx_IRQDISPATCH(6) +DEFINE_HWx_IRQDISPATCH(7) + void __init arch_init_irq(void) { #ifdef CONFIG_BCM47XX_BCMA @@ -64,4 +77,14 @@ void __init arch_init_irq(void) } #endif mips_cpu_irq_init(); + + if (cpu_has_vint) { + pr_info("Setting up vectored interrupts\n"); + set_vi_handler(2, bcm47xx_hw2_irqdispatch); + set_vi_handler(3, bcm47xx_hw3_irqdispatch); + set_vi_handler(4, bcm47xx_hw4_irqdispatch); + set_vi_handler(5, bcm47xx_hw5_irqdispatch); + set_vi_handler(6, bcm47xx_hw6_irqdispatch); + set_vi_handler(7, bcm47xx_hw7_irqdispatch); + } } |