diff options
| author | Yonghong Song <ysong@broadcom.com> | 2013-12-21 16:52:16 +0530 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2014-01-24 22:39:47 +0100 |
| commit | ed8dfc46e0099540cb923f61bca885b460f1365e (patch) | |
| tree | d7856bf6134c31844729669663a8d8917e74c4ae /arch/mips/pci | |
| parent | d3b94285025732379df8a46c02416400c70daa85 (diff) | |
MIPS: Netlogic: L1D cacheflush before thread enable on XLPII
On XLPII CPUs, the L1D cache has to be flushed with regular cache
operations before enabling threads in a core.
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6276/
Diffstat (limited to 'arch/mips/pci')
0 files changed, 0 insertions, 0 deletions