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authorRanjith Lohithakshan <ranjithl@ti.com>2010-03-31 04:16:30 -0600
committerPaul Walmsley <paul@pwsan.com>2010-03-31 04:16:30 -0600
commitd54a45e2533ef33678dc340298b022a289d2b3e3 (patch)
tree9e112f501b5695b2798dd78d3ec142d8eddfd97d /arch/mips/pci/fixup-rc32434.c
parent766d305fead341889e7b9611fdc97236075a29fb (diff)
OMAP3: clock: fix enable bit used for dpll4_m4x2 clock
The enable bit for dpll4_m4x2 clock should be OMAP3430_PWRDN_DSS1_SHIFT. The code erroneously uses OMAP3430_PWRDN_CAM_SHIFT which is meant for dpll4_m5x2 clock. This came into notice during a recent review of the clock tree. Signed-off-by: Ranjith Lohithakshan <ranjithl@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'arch/mips/pci/fixup-rc32434.c')
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