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authorLinus Torvalds <torvalds@linux-foundation.org>2013-09-12 16:14:49 -0700
committerLinus Torvalds <torvalds@linux-foundation.org>2013-09-12 16:14:49 -0700
commit5a7d8a28080caed7fd4cb1b81d092adac4445e8e (patch)
tree7d410cdd62dfebb24c22ccb8895efd9acf74ddb9 /arch/mips/kernel
parente0ea4045bce3cee84e35746fb98946ca36781248 (diff)
parenteb37e6ddf75a3d4c59e38193a7c8d409f5bd7d57 (diff)
Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
Pull MIPS updates from Ralf Baechle: "This has been sitting in -next for a while with no objections and all MIPS defconfigs except one are building fine; that one platform got broken by another patch in your tree and I'm going to submit a patch separately. - a handful of fixes that didn't make 3.11 - a few bits of Octeon 3 support with more to come for a later release - platform enhancements for Octeon, ath79, Lantiq, Netlogic and Ralink SOCs - a GPIO driver for the Octeon - some dusting off of the DECstation code - the usual dose of cleanups" * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (65 commits) MIPS: DMA: Fix BUG due to smp_processor_id() in preemptible code MIPS: kexec: Fix random crashes while loading crashkernel MIPS: kdump: Skip walking indirection page for crashkernels MIPS: DECstation HRT calibration bug fixes MIPS: Export copy_from_user_page() (needed by lustre) MIPS: Add driver for the built-in PCI controller of the RT3883 SoC MIPS: DMA: For BMIPS5000 cores flush region just like non-coherent R10000 MIPS: ralink: Add support for reset-controller API MIPS: ralink: mt7620: Add cpu-feature-override header MIPS: ralink: mt7620: Add spi clock definition MIPS: ralink: mt7620: Add wdt clock definition MIPS: ralink: mt7620: Improve clock frequency detection MIPS: ralink: mt7620: This SoC has EHCI and OHCI hosts MIPS: ralink: mt7620: Add verbose ram info MIPS: ralink: Probe clocksources from OF MIPS: ralink: Add support for systick timer found on newer ralink SoC MIPS: ralink: Add support for periodic timer irq MIPS: Netlogic: Built-in DTB for XLP2xx SoC boards MIPS: Netlogic: Add support for USB on XLP2xx MIPS: Netlogic: XLP2xx update for I2C controller ...
Diffstat (limited to 'arch/mips/kernel')
-rw-r--r--arch/mips/kernel/cpu-probe.c12
-rw-r--r--arch/mips/kernel/csrc-ioasic.c6
-rw-r--r--arch/mips/kernel/idle.c1
-rw-r--r--arch/mips/kernel/mcount.S2
-rw-r--r--arch/mips/kernel/relocate_kernel.S6
-rw-r--r--arch/mips/kernel/setup.c99
-rw-r--r--arch/mips/kernel/time.c10
-rw-r--r--arch/mips/kernel/vmlinux.lds.S1
8 files changed, 81 insertions, 56 deletions
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 4c6167a17875..37663c7862a5 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -852,10 +852,17 @@ platform:
case PRID_IMP_CAVIUM_CN63XX:
case PRID_IMP_CAVIUM_CN66XX:
case PRID_IMP_CAVIUM_CN68XX:
+ case PRID_IMP_CAVIUM_CNF71XX:
c->cputype = CPU_CAVIUM_OCTEON2;
__cpu_name[cpu] = "Cavium Octeon II";
set_elf_platform(cpu, "octeon2");
break;
+ case PRID_IMP_CAVIUM_CN70XX:
+ case PRID_IMP_CAVIUM_CN78XX:
+ c->cputype = CPU_CAVIUM_OCTEON3;
+ __cpu_name[cpu] = "Cavium Octeon III";
+ set_elf_platform(cpu, "octeon3");
+ break;
default:
printk(KERN_INFO "Unknown Octeon chip!\n");
c->cputype = CPU_UNKNOWN;
@@ -899,6 +906,11 @@ static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
MIPS_CPU_LLSC);
switch (c->processor_id & 0xff00) {
+ case PRID_IMP_NETLOGIC_XLP2XX:
+ c->cputype = CPU_XLP;
+ __cpu_name[cpu] = "Broadcom XLPII";
+ break;
+
case PRID_IMP_NETLOGIC_XLP8XX:
case PRID_IMP_NETLOGIC_XLP3XX:
c->cputype = CPU_XLP;
diff --git a/arch/mips/kernel/csrc-ioasic.c b/arch/mips/kernel/csrc-ioasic.c
index 0654bff9b69c..87e88feb4a25 100644
--- a/arch/mips/kernel/csrc-ioasic.c
+++ b/arch/mips/kernel/csrc-ioasic.c
@@ -41,9 +41,9 @@ void __init dec_ioasic_clocksource_init(void)
{
unsigned int freq;
u32 start, end;
- int i = HZ / 10;
-
+ int i = HZ / 8;
+ ds1287_timer_state();
while (!ds1287_timer_state())
;
@@ -55,7 +55,7 @@ void __init dec_ioasic_clocksource_init(void)
end = dec_ioasic_hpt_read(&clocksource_dec);
- freq = (end - start) * 10;
+ freq = (end - start) * 8;
printk(KERN_INFO "I/O ASIC clock frequency %dHz\n", freq);
clocksource_dec.rating = 200 + freq / 10000000;
diff --git a/arch/mips/kernel/idle.c b/arch/mips/kernel/idle.c
index 0c655deeea4a..42f8875d2444 100644
--- a/arch/mips/kernel/idle.c
+++ b/arch/mips/kernel/idle.c
@@ -166,6 +166,7 @@ void __init check_wait(void)
case CPU_CAVIUM_OCTEON:
case CPU_CAVIUM_OCTEON_PLUS:
case CPU_CAVIUM_OCTEON2:
+ case CPU_CAVIUM_OCTEON3:
case CPU_JZRISC:
case CPU_LOONGSON1:
case CPU_XLR:
diff --git a/arch/mips/kernel/mcount.S b/arch/mips/kernel/mcount.S
index a03e93c4a946..539b6294b613 100644
--- a/arch/mips/kernel/mcount.S
+++ b/arch/mips/kernel/mcount.S
@@ -83,7 +83,7 @@ _mcount:
PTR_S MCOUNT_RA_ADDRESS_REG, PT_R12(sp)
#endif
- move a0, ra /* arg1: self return address */
+ PTR_SUBU a0, ra, 8 /* arg1: self address */
.globl ftrace_call
ftrace_call:
nop /* a placeholder for the call to a real tracing function */
diff --git a/arch/mips/kernel/relocate_kernel.S b/arch/mips/kernel/relocate_kernel.S
index 43d2d78d3287..74bab9ddd0e1 100644
--- a/arch/mips/kernel/relocate_kernel.S
+++ b/arch/mips/kernel/relocate_kernel.S
@@ -26,6 +26,12 @@ process_entry:
PTR_L s2, (s0)
PTR_ADD s0, s0, SZREG
+ /*
+ * In case of a kdump/crash kernel, the indirection page is not
+ * populated as the kernel is directly copied to a reserved location
+ */
+ beqz s2, done
+
/* destination page */
and s3, s2, 0x1
beq s3, zero, 1f
diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c
index c7f90519e58c..c538d6e01b7b 100644
--- a/arch/mips/kernel/setup.c
+++ b/arch/mips/kernel/setup.c
@@ -552,6 +552,52 @@ static void __init arch_mem_addpart(phys_t mem, phys_t end, int type)
add_memory_region(mem, size, type);
}
+#ifdef CONFIG_KEXEC
+static inline unsigned long long get_total_mem(void)
+{
+ unsigned long long total;
+
+ total = max_pfn - min_low_pfn;
+ return total << PAGE_SHIFT;
+}
+
+static void __init mips_parse_crashkernel(void)
+{
+ unsigned long long total_mem;
+ unsigned long long crash_size, crash_base;
+ int ret;
+
+ total_mem = get_total_mem();
+ ret = parse_crashkernel(boot_command_line, total_mem,
+ &crash_size, &crash_base);
+ if (ret != 0 || crash_size <= 0)
+ return;
+
+ crashk_res.start = crash_base;
+ crashk_res.end = crash_base + crash_size - 1;
+}
+
+static void __init request_crashkernel(struct resource *res)
+{
+ int ret;
+
+ ret = request_resource(res, &crashk_res);
+ if (!ret)
+ pr_info("Reserving %ldMB of memory at %ldMB for crashkernel\n",
+ (unsigned long)((crashk_res.end -
+ crashk_res.start + 1) >> 20),
+ (unsigned long)(crashk_res.start >> 20));
+}
+#else /* !defined(CONFIG_KEXEC) */
+static void __init mips_parse_crashkernel(void)
+{
+}
+
+static void __init request_crashkernel(struct resource *res)
+{
+}
+#endif /* !defined(CONFIG_KEXEC) */
+
static void __init arch_mem_init(char **cmdline_p)
{
extern void plat_mem_setup(void);
@@ -608,6 +654,8 @@ static void __init arch_mem_init(char **cmdline_p)
BOOTMEM_DEFAULT);
}
#endif
+
+ mips_parse_crashkernel();
#ifdef CONFIG_KEXEC
if (crashk_res.start != crashk_res.end)
reserve_bootmem(crashk_res.start,
@@ -620,52 +668,6 @@ static void __init arch_mem_init(char **cmdline_p)
paging_init();
}
-#ifdef CONFIG_KEXEC
-static inline unsigned long long get_total_mem(void)
-{
- unsigned long long total;
-
- total = max_pfn - min_low_pfn;
- return total << PAGE_SHIFT;
-}
-
-static void __init mips_parse_crashkernel(void)
-{
- unsigned long long total_mem;
- unsigned long long crash_size, crash_base;
- int ret;
-
- total_mem = get_total_mem();
- ret = parse_crashkernel(boot_command_line, total_mem,
- &crash_size, &crash_base);
- if (ret != 0 || crash_size <= 0)
- return;
-
- crashk_res.start = crash_base;
- crashk_res.end = crash_base + crash_size - 1;
-}
-
-static void __init request_crashkernel(struct resource *res)
-{
- int ret;
-
- ret = request_resource(res, &crashk_res);
- if (!ret)
- pr_info("Reserving %ldMB of memory at %ldMB for crashkernel\n",
- (unsigned long)((crashk_res.end -
- crashk_res.start + 1) >> 20),
- (unsigned long)(crashk_res.start >> 20));
-}
-#else /* !defined(CONFIG_KEXEC) */
-static void __init mips_parse_crashkernel(void)
-{
-}
-
-static void __init request_crashkernel(struct resource *res)
-{
-}
-#endif /* !defined(CONFIG_KEXEC) */
-
static void __init resource_init(void)
{
int i;
@@ -678,11 +680,6 @@ static void __init resource_init(void)
data_resource.start = __pa_symbol(&_etext);
data_resource.end = __pa_symbol(&_edata) - 1;
- /*
- * Request address space for all standard RAM.
- */
- mips_parse_crashkernel();
-
for (i = 0; i < boot_mem_map.nr_map; i++) {
struct resource *res;
unsigned long start, end;
diff --git a/arch/mips/kernel/time.c b/arch/mips/kernel/time.c
index 9d686bf97b0e..364d26ae4215 100644
--- a/arch/mips/kernel/time.c
+++ b/arch/mips/kernel/time.c
@@ -121,6 +121,14 @@ void __init time_init(void)
{
plat_time_init();
- if (!mips_clockevent_init() || !cpu_has_mfc0_count_bug())
+ /*
+ * The use of the R4k timer as a clock event takes precedence;
+ * if reading the Count register might interfere with the timer
+ * interrupt, then we don't use the timer as a clock source.
+ * We may still use the timer as a clock source though if the
+ * timer interrupt isn't reliable; the interference doesn't
+ * matter then, because we don't use the interrupt.
+ */
+ if (mips_clockevent_init() != 0 || !cpu_has_mfc0_count_bug())
init_mips_clocksource();
}
diff --git a/arch/mips/kernel/vmlinux.lds.S b/arch/mips/kernel/vmlinux.lds.S
index 05826d20a792..3b46f7ce9ca7 100644
--- a/arch/mips/kernel/vmlinux.lds.S
+++ b/arch/mips/kernel/vmlinux.lds.S
@@ -179,5 +179,6 @@ SECTIONS
*(.options)
*(.pdr)
*(.reginfo)
+ *(.eh_frame)
}
}