[MIPS] Handle R4000/R4400 mfc0 from count register.

The R4000 and R4400 have an errata where if the cp0 count register is read
in the exact moment when it matches the compare register no interrupt will
be generated.

This bug may be triggered if the cp0 count register is being used as
clocksource and the compare interrupt as clockevent.  So a simple
workaround is to avoid using the compare for both facilities on the
affected CPUs.

This is different from the workaround suggested in the old errata documents;
at some opportunity probably the official version should be implemented
and tested.  Another thing to find out is which processor versions
exactly are affected.  I only have errata documents upto R4400 V3.0
available so for the moment the code treats all R4000 and R4400 as broken.

This is potencially a problem for some machines that have no other decent
clocksource available; this workaround will cause them to fall back to
another clocksource, worst case the "jiffies" source.

1 files changed, 7 insertions, 5 deletions

diff --git a/arch/mips/kernel/cevt-r4k.c b/arch/mips/kernel/cevt-r4k.c
index 076f52b9bb79..24a2d907aa0d 100644
--- a/arch/mips/kernel/cevt-r4k.c
+++ b/arch/mips/kernel/cevt-r4k.c
@@ -219,7 +219,7 @@ static int c0_compare_int_usable(void)
 	return 1;
 }
 
-void __cpuinit mips_clockevent_init(void)
+int __cpuinit mips_clockevent_init(void)
 {
 	uint64_t mips_freq = mips_hpt_frequency;
 	unsigned int cpu = smp_processor_id();
@@ -227,7 +227,7 @@ void __cpuinit mips_clockevent_init(void)
 	unsigned int irq;
 
 	if (!cpu_has_counter || !mips_hpt_frequency)
-		return;
+		return -ENXIO;
 
 #ifdef CONFIG_MIPS_MT_SMTC
 	setup_smtc_dummy_clockevent_device();
@@ -237,11 +237,11 @@ void __cpuinit mips_clockevent_init(void)
 	 * device.
 	 */
 	if (cpu)
-		return;
+		return 0;
 #endif
 
 	if (!c0_compare_int_usable())
-		return;
+		return -ENXIO;
 
 	/*
 	 * With vectored interrupts things are getting platform specific.
@@ -277,7 +277,7 @@ void __cpuinit mips_clockevent_init(void)
 	clockevents_register_device(cd);
 
 	if (cp0_timer_irq_installed)
-		return;
+		return 0;
 
 	cp0_timer_irq_installed = 1;
 
@@ -287,4 +287,6 @@ void __cpuinit mips_clockevent_init(void)
 #else
 	setup_irq(irq, &c0_compare_irqaction);
 #endif
+
+	return 0;
 }