diff options
| author | Xiang Chen <chenxiang66@hisilicon.com> | 2017-06-14 23:33:24 +0800 |
|---|---|---|
| committer | Martin K. Petersen <martin.petersen@oracle.com> | 2017-06-19 21:31:26 -0400 |
| commit | 60b4a5ee90349a50fc7e199d3dd37dfd7e2c51a5 (patch) | |
| tree | cf630fb96d1785b724ef944699ac85361d835b7e /arch/mips/kernel/cacheinfo.c | |
| parent | 54edeee1e1f3621632308212daf383ed6688e955 (diff) | |
scsi: hisi_sas: add v3 cq interrupt handler
Add v3 cq interrupt handler slot_complete_v3_hw().
Note: The slot error handling needs to be further refined in the future
to examine all fields in the error record, and handle appropriately,
instead of current solution - just report SAS_OPEN_REJECT.
Signed-off-by: John Garry <john.garry@huawei.com>
Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
Diffstat (limited to 'arch/mips/kernel/cacheinfo.c')
0 files changed, 0 insertions, 0 deletions