diff options
| author | Gabor Juhos <juhosg@openwrt.org> | 2013-08-23 15:06:36 +0200 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2013-09-04 16:58:31 +0200 |
| commit | 9852ba6a914f95db65e86fed85d02d5309a301da (patch) | |
| tree | e2bce37be0c3e28fd614d619aabfb9e209226327 /arch/mips/include | |
| parent | 0d4649684ca6cbc536fcc509e7aac0b34bb4146a (diff) | |
MIPS: ralink: mt7620: Add cpu-feature-override header
Override certain CPU features to help GCC to optimize
the generated code. Saves about 150KB in the vmlinux
image with a generic configuration.
text data bss dec hex filename
3824158 134820 234192 4193170 3ffb92 vmlinux.no-override
3664054 138804 234192 4037050 3d99ba vmlinux.override
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5759/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include')
| -rw-r--r-- | arch/mips/include/asm/mach-ralink/mt7620/cpu-feature-overrides.h | 57 |
1 files changed, 57 insertions, 0 deletions
diff --git a/arch/mips/include/asm/mach-ralink/mt7620/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ralink/mt7620/cpu-feature-overrides.h new file mode 100644 index 000000000000..f7bb8cfc5eb1 --- /dev/null +++ b/arch/mips/include/asm/mach-ralink/mt7620/cpu-feature-overrides.h @@ -0,0 +1,57 @@ +/* + * Ralink MT7620 specific CPU feature overrides + * + * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> + * + * This file was derived from: include/asm-mips/cpu-features.h + * Copyright (C) 2003, 2004 Ralf Baechle + * Copyright (C) 2004 Maciej W. Rozycki + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ +#ifndef _MT7620_CPU_FEATURE_OVERRIDES_H +#define _MT7620_CPU_FEATURE_OVERRIDES_H + +#define cpu_has_tlb 1 +#define cpu_has_4kex 1 +#define cpu_has_3k_cache 0 +#define cpu_has_4k_cache 1 +#define cpu_has_tx39_cache 0 +#define cpu_has_sb1_cache 0 +#define cpu_has_fpu 0 +#define cpu_has_32fpr 0 +#define cpu_has_counter 1 +#define cpu_has_watch 1 +#define cpu_has_divec 1 + +#define cpu_has_prefetch 1 +#define cpu_has_ejtag 1 +#define cpu_has_llsc 1 + +#define cpu_has_mips16 1 +#define cpu_has_mdmx 0 +#define cpu_has_mips3d 0 +#define cpu_has_smartmips 0 + +#define cpu_has_mips32r1 1 +#define cpu_has_mips32r2 1 +#define cpu_has_mips64r1 0 +#define cpu_has_mips64r2 0 + +#define cpu_has_dsp 1 +#define cpu_has_dsp2 0 +#define cpu_has_mipsmt 0 + +#define cpu_has_64bits 0 +#define cpu_has_64bit_zero_reg 0 +#define cpu_has_64bit_gp_regs 0 +#define cpu_has_64bit_addresses 0 + +#define cpu_dcache_line_size() 32 +#define cpu_icache_line_size() 32 + +#endif /* _MT7620_CPU_FEATURE_OVERRIDES_H */ |