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authorDavid Daney <ddaney@avtrex.com>2008-09-23 00:05:54 -0700
committerRalf Baechle <ralf@linux-mips.org>2008-10-11 16:18:56 +0100
commit6aa3524c182c01b8b8b7c21c4da20c742a9b4d86 (patch)
tree245fc4e9f26ad9e7a95e83087bfcc79528d1352e /arch/mips/include/asm/thread_info.h
parent8192c9ea9ac44213d1266ecb64615519443979b3 (diff)
MIPS: Add HARDWARE_WATCHPOINTS definitions and support code.
This is the main support code for the patch. Here we just add the code, the following patches hook it up. Signed-off-by: David Daney <ddaney@avtrex.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> create mode 100644 arch/mips/include/asm/watch.h create mode 100644 arch/mips/kernel/watch.c
Diffstat (limited to 'arch/mips/include/asm/thread_info.h')
-rw-r--r--arch/mips/include/asm/thread_info.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/mips/include/asm/thread_info.h b/arch/mips/include/asm/thread_info.h
index bb3060699df2..3f76de73c943 100644
--- a/arch/mips/include/asm/thread_info.h
+++ b/arch/mips/include/asm/thread_info.h
@@ -124,6 +124,7 @@ register struct thread_info *__current_thread_info __asm__("$28");
#define TIF_32BIT_REGS 22 /* also implies 16/32 fprs */
#define TIF_32BIT_ADDR 23 /* 32-bit address space (o32/n32) */
#define TIF_FPUBOUND 24 /* thread bound to FPU-full CPU set */
+#define TIF_LOAD_WATCH 25 /* If set, load watch registers */
#define TIF_SYSCALL_TRACE 31 /* syscall trace active */
#define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE)
@@ -140,6 +141,7 @@ register struct thread_info *__current_thread_info __asm__("$28");
#define _TIF_32BIT_REGS (1<<TIF_32BIT_REGS)
#define _TIF_32BIT_ADDR (1<<TIF_32BIT_ADDR)
#define _TIF_FPUBOUND (1<<TIF_FPUBOUND)
+#define _TIF_LOAD_WATCH (1<<TIF_LOAD_WATCH)
/* work to do on interrupt/exception return */
#define _TIF_WORK_MASK (0x0000ffef & ~_TIF_SECCOMP)