diff options
| author | Ralf Baechle <ralf@linux-mips.org> | 2005-09-03 15:56:17 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@evo.osdl.org> | 2005-09-05 00:06:07 -0700 |
| commit | 42a3b4f25af8f8d77feddf27f839fa0628dbff1a (patch) | |
| tree | 332370ff3889fabb66a45fb5dcf605b142de77c8 /arch/mips/ddb5xxx/ddb5477/irq.c | |
| parent | 875d43e72b5bf22161a81de7554f88eccf8a51ae (diff) | |
[PATCH] mips: nuke trailing whitespace
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'arch/mips/ddb5xxx/ddb5477/irq.c')
| -rw-r--r-- | arch/mips/ddb5xxx/ddb5477/irq.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/mips/ddb5xxx/ddb5477/irq.c b/arch/mips/ddb5xxx/ddb5477/irq.c index 5f027bfa4af8..9ffe1a9142ca 100644 --- a/arch/mips/ddb5xxx/ddb5477/irq.c +++ b/arch/mips/ddb5xxx/ddb5477/irq.c @@ -76,7 +76,7 @@ set_pci_int_attr(u32 pci, u32 intn, u32 active, u32 trigger) extern void vrc5477_irq_init(u32 base); extern void mips_cpu_irq_init(u32 base); extern asmlinkage void ddb5477_handle_int(void); -extern int setup_irq(unsigned int irq, struct irqaction *irqaction); +extern int setup_irq(unsigned int irq, struct irqaction *irqaction); static struct irqaction irq_cascade = { no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL }; void __init arch_init_irq(void) @@ -94,7 +94,7 @@ void __init arch_init_irq(void) /* setup PCI interrupt attributes */ set_pci_int_attr(PCI0, INTA, ACTIVE_LOW, LEVEL_SENSE); set_pci_int_attr(PCI0, INTB, ACTIVE_LOW, LEVEL_SENSE); - if (mips_machtype == MACH_NEC_ROCKHOPPERII) + if (mips_machtype == MACH_NEC_ROCKHOPPERII) set_pci_int_attr(PCI0, INTC, ACTIVE_HIGH, LEVEL_SENSE); else set_pci_int_attr(PCI0, INTC, ACTIVE_LOW, LEVEL_SENSE); @@ -134,7 +134,7 @@ void __init arch_init_irq(void) /* setup cascade interrupts */ setup_irq(VRC5477_IRQ_BASE + VRC5477_I8259_CASCADE, &irq_cascade); - setup_irq(CPU_IRQ_BASE + CPU_VRC5477_CASCADE, &irq_cascade); + setup_irq(CPU_IRQ_BASE + CPU_VRC5477_CASCADE, &irq_cascade); /* hook up the first-level interrupt handler */ set_except_vector(0, ddb5477_handle_int); |