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authorSteven J. Hill <sjhill@mips.com>2012-11-14 23:34:17 -0600
committerRalf Baechle <ralf@linux-mips.org>2012-12-13 18:15:24 +0100
commitd7ea335c05ba7c013615d1e0d5a71459eb4195e8 (patch)
tree333f0cb8edd150b6c967bffacad07c03fea393da /arch/mips/Kconfig
parentdcb96a4e36425d563cefd44a20d3386e02a547f3 (diff)
MIPS: Remove usage of CSRC_R4K_LIB config option.
Manuel Lauss <manuel.lauss@gmail.com> writes: I introduced it as a fallback because early revisions of Alchemy hardware we shipped had a non-functional 32kHz timer and had to rely on the r4k timer instead. Previously the r4k timer was initialized regardless, but it's useless with the "wait" instruction. So long story short: I need either the on-chip 32kHz timer OR the r4k timer if the 32kHz one is unusable, but not both, and r4k timer is useless when au1k_idle is in use. The current in-kernel Alchemy boards all work with the 32kHz timer, so I'm not against removing R4K_LIB symbols. Signed-off-by: Steven J. Hill <sjhill@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/Kconfig')
-rw-r--r--arch/mips/Kconfig6
1 files changed, 1 insertions, 5 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 9b3759eef953..b04b4916aa3d 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -55,7 +55,7 @@ config MIPS_ALCHEMY
bool "Alchemy processor based machines"
select 64BIT_PHYS_ADDR
select CEVT_R4K_LIB
- select CSRC_R4K_LIB
+ select CSRC_R4K
select IRQ_CPU
select SYS_HAS_CPU_MIPS32_R1
select SYS_SUPPORTS_32BIT_KERNEL
@@ -948,11 +948,7 @@ config CSRC_IOASIC
config CSRC_POWERTV
bool
-config CSRC_R4K_LIB
- bool
-
config CSRC_R4K
- select CSRC_R4K_LIB
bool
config CSRC_SB1250