diff options
| author | Greg Ungerer <gerg@uclinux.org> | 2011-12-24 12:32:52 +1000 |
|---|---|---|
| committer | Greg Ungerer <gerg@uclinux.org> | 2012-03-05 09:43:09 +1000 |
| commit | a4e2e2ac08f73dedeabecb9e1141a05889591b7b (patch) | |
| tree | 649af490d48b9cc406e5c5709717add5ee6e2697 /arch/m68k/include/asm/m520xsim.h | |
| parent | b7ce7f0d0efc1a95154fa6872d5d7c970d281c71 (diff) | |
m68knommu: make 520x QSPI platform addressing consistent
If we make all QSPI (SPI protocol) addressing consistent across all ColdFire
family members then we will be able to remove the duplicated plaform data
and code and use a single setup for all.
So modify the ColdFire 520x QSPI addressing so that:
. base addresses are absolute (not relative to MBAR peripheral register)
. use a common name for IRQs used
. move chip select definitions (CS) to appropriate header
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Diffstat (limited to 'arch/m68k/include/asm/m520xsim.h')
| -rw-r--r-- | arch/m68k/include/asm/m520xsim.h | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/m68k/include/asm/m520xsim.h b/arch/m68k/include/asm/m520xsim.h index b83cee2dfdac..17f2aab9cf97 100644 --- a/arch/m68k/include/asm/m520xsim.h +++ b/arch/m68k/include/asm/m520xsim.h @@ -61,6 +61,8 @@ #define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0) #define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0) +#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI) + /* * SDRAM configuration registers. */ @@ -166,6 +168,16 @@ #define MCFFEC_SIZE0 0x800 /* Register set size */ /* + * QSPI module. + */ +#define MCFQSPI_BASE 0xFC05C000 /* Base of QSPI module */ +#define MCFQSPI_SIZE 0x40 /* Register set size */ + +#define MCFQSPI_CS0 46 +#define MCFQSPI_CS1 47 +#define MCFQSPI_CS2 27 + +/* * Reset Control Unit. */ #define MCF_RCR 0xFC0A0000 |