diff options
| author | Tony Luck <tony.luck@intel.com> | 2008-10-17 13:47:53 -0700 |
|---|---|---|
| committer | Tony Luck <tony.luck@intel.com> | 2008-10-17 13:47:53 -0700 |
| commit | a9894a4a3c7fb53258d46dafe9dd4f45369fd9dd (patch) | |
| tree | 9c82955ea3039980ad3432ccb1801cdb66e112c5 /arch/ia64/include/asm | |
| parent | 26e9a397774a0e94efbb8a0bf4a952c28d808cab (diff) | |
[IA64] Fix annoying IA64_TR_ALLOC_MAX message.
Madison cpus support 64 TR registers. Increase IA64_TR_ALLOC_MAX
to 64. Also fixup the messages that get printed when this limit
is exceeded. Repeating for every cpu is too noisy.
Signed-off-by: Tony Luck <tony.luck@intel.com>
Diffstat (limited to 'arch/ia64/include/asm')
| -rw-r--r-- | arch/ia64/include/asm/kregs.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/ia64/include/asm/kregs.h b/arch/ia64/include/asm/kregs.h index aefcdfee7f23..39e65f6639f5 100644 --- a/arch/ia64/include/asm/kregs.h +++ b/arch/ia64/include/asm/kregs.h @@ -32,7 +32,7 @@ #define IA64_TR_CURRENT_STACK 1 /* dtr1: maps kernel's memory- & register-stacks */ #define IA64_TR_ALLOC_BASE 2 /* itr&dtr: Base of dynamic TR resource*/ -#define IA64_TR_ALLOC_MAX 32 /* Max number for dynamic use*/ +#define IA64_TR_ALLOC_MAX 64 /* Max number for dynamic use*/ /* Processor status register bits: */ #define IA64_PSR_BE_BIT 1 |