diff options
| author | Guo Ren <ren_guo@c-sky.com> | 2019-06-18 17:20:10 +0800 |
|---|---|---|
| committer | Guo Ren <ren_guo@c-sky.com> | 2019-07-19 14:21:36 +0800 |
| commit | 9d35dc3006a9865eb5b55cc79df49933601131f8 (patch) | |
| tree | 6f16dbd7f5111bcea394079e199bb68701459235 /arch/csky/kernel | |
| parent | 4d581034f9086f784a3408575bdb3c201740c6cb (diff) | |
csky: Revert mmu ASID mechanism
Current C-SKY ASID mechanism is from mips and it doesn't work well
with multi-cores. ASID per core mechanism is not suitable for C-SKY
SMP tlb maintain operations, eg: tlbi.vas need share the same asid
in all processors and it'll invalid the tlb entry in all cores with
the same asid.
This patch is prepare for new ASID mechanism.
Signed-off-by: Guo Ren <ren_guo@c-sky.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/csky/kernel')
| -rw-r--r-- | arch/csky/kernel/smp.c | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/arch/csky/kernel/smp.c b/arch/csky/kernel/smp.c index b07a534b3062..b753d382e4ce 100644 --- a/arch/csky/kernel/smp.c +++ b/arch/csky/kernel/smp.c @@ -212,8 +212,6 @@ void csky_start_secondary(void) TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir); TLBMISS_HANDLER_SETUP_PGD_KERNEL(swapper_pg_dir); - asid_cache(smp_processor_id()) = ASID_FIRST_VERSION; - #ifdef CONFIG_CPU_HAS_FPU init_fpu(); #endif |