diff options
| author | Guo Ren <guoren@linux.alibaba.com> | 2020-12-24 05:59:57 +0000 |
|---|---|---|
| committer | Guo Ren <guoren@linux.alibaba.com> | 2021-01-12 09:52:41 +0800 |
| commit | 3b756ccddb8a75563900cd603c83160b43f3d691 (patch) | |
| tree | af6428140af2760616d577a0b1e515a45b58207c /arch/csky/abiv1 | |
| parent | c109f42450ec25283169dd6c0acce8d053493732 (diff) | |
csky: Fix TLB maintenance synchronization problem
TLB invalidate didn't contain a barrier operation in csky cpu and
we need to prevent previous PTW response after TLB invalidation
instruction. Of cause, the ASID changing also needs to take care
of the issue.
CPU0 CPU1
=============== ===============
set_pte
sync_is() -> See the previous set_pte for all harts
tlbi.vas -> Invalidate all harts TLB entry & flush pipeline
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Diffstat (limited to 'arch/csky/abiv1')
| -rw-r--r-- | arch/csky/abiv1/inc/abi/ckmmu.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/csky/abiv1/inc/abi/ckmmu.h b/arch/csky/abiv1/inc/abi/ckmmu.h index cceb3afb4c91..b4650de43078 100644 --- a/arch/csky/abiv1/inc/abi/ckmmu.h +++ b/arch/csky/abiv1/inc/abi/ckmmu.h @@ -89,9 +89,10 @@ static inline void tlb_invalid_indexed(void) cpwcr("cpcr8", 0x02000000); } -static inline void setup_pgd(pgd_t *pgd) +static inline void setup_pgd(pgd_t *pgd, int asid) { cpwcr("cpcr29", __pa(pgd) | BIT(0)); + write_mmu_entryhi(asid); } static inline pgd_t *get_pgd(void) |