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authorRussell King <rmk@dyn-67.arm.linux.org.uk>2005-07-29 16:36:48 +0100
committerRussell King <rmk+kernel@arm.linux.org.uk>2005-07-29 16:36:48 +0100
commit7ac5ae4b122f9415948c642b945a26938aa8f347 (patch)
treed925c9b022866bfac4e1e0ddaff76cbe158bdbbf /arch/arm
parente7ec02938dbe8ca35b750f29eaa4b12de0b52754 (diff)
[ARM SMP] Ensure secondary CPUs see their pen release
Since the secondary CPUs will not be operating in symetric mode while they are held in the pen, we need to ensure that the write to pen_release is visible to them, by flushing the cache. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/mach-integrator/platsmp.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/mach-integrator/platsmp.c b/arch/arm/mach-integrator/platsmp.c
index aecf47ba033a..ea10bd8c972c 100644
--- a/arch/arm/mach-integrator/platsmp.c
+++ b/arch/arm/mach-integrator/platsmp.c
@@ -15,6 +15,7 @@
#include <linux/mm.h>
#include <asm/atomic.h>
+#include <asm/cacheflush.h>
#include <asm/delay.h>
#include <asm/mmu_context.h>
#include <asm/procinfo.h>
@@ -80,6 +81,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
* "cpu" is Linux's internal ID.
*/
pen_release = cpu;
+ flush_cache_all();
/*
* XXX