diff options
| author | Shawn Guo <shawn.guo@linaro.org> | 2013-10-31 10:35:40 +0800 |
|---|---|---|
| committer | Shawn Guo <shawn.guo@linaro.org> | 2013-11-11 22:58:43 +0800 |
| commit | 2c11b57a8a8d83ffa91aebb12c90488c8802e6f3 (patch) | |
| tree | a3163627418de04d98d2a0ed2480624e248902e8 /arch/arm | |
| parent | b6e23bb63f28f0a8ffa7cf9824fa48000c08f9b2 (diff) | |
ARM: imx: improve mxc_restart() on the SRC bit writes
The current comment in the code does not make it clear why the double writes
on SRC bit is needed. Let's quote the errata to get it clear. Also, to
ensure there are at least 2 writes happen in the same one 32kHz period,
we actually need 3 writes. Let's add the third one.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/mach-imx/system.c | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/arch/arm/mach-imx/system.c b/arch/arm/mach-imx/system.c index 826b72ba08d9..5e3027d3692f 100644 --- a/arch/arm/mach-imx/system.c +++ b/arch/arm/mach-imx/system.c @@ -52,7 +52,14 @@ void mxc_restart(enum reboot_mode mode, const char *cmd) /* Assert SRS signal */ __raw_writew(wcr_enable, wdog_base); - /* write twice to ensure the request will not get ignored */ + /* + * Due to imx6q errata ERR004346 (WDOG: WDOG SRS bit requires to be + * written twice), we add another two writes to ensure there must be at + * least two writes happen in the same one 32kHz clock period. We save + * the target check here, since the writes shouldn't be a huge burden + * for other platforms. + */ + __raw_writew(wcr_enable, wdog_base); __raw_writew(wcr_enable, wdog_base); /* wait for reset to assert... */ |