diff options
| author | Nicolas Pitre <nico@cam.org> | 2006-02-01 19:26:01 +0000 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2006-02-01 19:26:01 +0000 |
| commit | 18afea04f1dfc5d52fd2579cd17adc3956acd4ad (patch) | |
| tree | 45b56a2a6c16662bfd135637295798a9fba3ac69 /arch/arm | |
| parent | 8a052e0bc25ff52f17b3dff150846ca9eb969162 (diff) | |
[ARM] 3294/1: don't invalidate individual BTB entries on ARMv6
Patch from Nicolas Pitre
Doing so adds a much larger cost to the loop than the cost implied by
simply invalidating the whole BTB at once.
Signed-off-by: Nicolas Pitre <nico@cam.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/mm/cache-v6.S | 18 |
1 files changed, 6 insertions, 12 deletions
diff --git a/arch/arm/mm/cache-v6.S b/arch/arm/mm/cache-v6.S index 72966d90e956..d921c1024ae0 100644 --- a/arch/arm/mm/cache-v6.S +++ b/arch/arm/mm/cache-v6.S @@ -92,22 +92,16 @@ ENTRY(v6_coherent_kern_range) * - the Icache does not read data from the write buffer */ ENTRY(v6_coherent_user_range) - bic r0, r0, #CACHE_LINE_SIZE - 1 -1: + #ifdef HARVARD_CACHE - mcr p15, 0, r0, c7, c10, 1 @ clean D line + bic r0, r0, #CACHE_LINE_SIZE - 1 +1: mcr p15, 0, r0, c7, c10, 1 @ clean D line mcr p15, 0, r0, c7, c5, 1 @ invalidate I line -#endif - mcr p15, 0, r0, c7, c5, 7 @ invalidate BTB entry - add r0, r0, #BTB_FLUSH_SIZE - mcr p15, 0, r0, c7, c5, 7 @ invalidate BTB entry - add r0, r0, #BTB_FLUSH_SIZE - mcr p15, 0, r0, c7, c5, 7 @ invalidate BTB entry - add r0, r0, #BTB_FLUSH_SIZE - mcr p15, 0, r0, c7, c5, 7 @ invalidate BTB entry - add r0, r0, #BTB_FLUSH_SIZE + add r0, r0, #CACHE_LINE_SIZE cmp r0, r1 blo 1b +#endif + mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB #ifdef HARVARD_CACHE mov r0, #0 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer |