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authorHeiko Stuebner <heiko@sntech.de>2018-08-22 14:09:25 +0200
committerHeiko Stuebner <heiko@sntech.de>2019-10-10 23:19:30 +0200
commit87d8ae980e1944331f93e0488e16bd3bec4554c7 (patch)
treea2ac4249cb87d5bd25025f98a35fe611fa564031 /arch/arm64
parent6860769ea771cf7fdb77c0f1333096c9700be141 (diff)
arm64: dts: rockchip: add cr50 tpm to rk3399-gru scarlet and bob
Scarlet and Bob use the Google-developed cr50 chip to do things like TPM and closed-case-debugging. Add the nodes describing the cr50 and its spi-connection. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20180822120925.12388-1-heiko@sntech.de
Diffstat (limited to 'arch/arm64')
-rw-r--r--arch/arm64/boot/dts/rockchip/rk3399-gru-bob.dts10
-rw-r--r--arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi10
2 files changed, 20 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-bob.dts b/arch/arm64/boot/dts/rockchip/rk3399-gru-bob.dts
index a9f4d6d7d2b7..9dd3b171e91d 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-gru-bob.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-bob.dts
@@ -68,6 +68,16 @@
&spi0 {
status = "okay";
+
+ cr50@0 {
+ compatible = "google,cr50";
+ reg = <0>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <5 IRQ_TYPE_EDGE_RISING>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&h1_int_od_l>;
+ spi-max-frequency = <800000>;
+ };
};
&pinctrl {
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi
index 50dfab51f175..4373ed732af7 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi
@@ -436,6 +436,16 @@ camera: &i2c7 {
&spi2 {
status = "okay";
+
+ cr50@0 {
+ compatible = "google,cr50";
+ reg = <0>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <17 IRQ_TYPE_EDGE_RISING>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&h1_int_od_l>;
+ spi-max-frequency = <800000>;
+ };
};
&usb_host0_ohci {