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authorNeil Armstrong <narmstrong@baylibre.com>2020-03-13 10:07:12 +0100
committerKevin Hilman <khilman@baylibre.com>2020-03-17 15:15:08 -0700
commit0e1610e726d33f3bce1057470569acc96032a074 (patch)
tree5ef2e36867a23d11ceeaa0b4fec0f62811ae7c99 /arch/arm64
parentf12a463d2f43b9c87fcf9d53615491f23ad44529 (diff)
arm64: dts: khadas-vim3: add SPIFC controller node
Add disabled SPIFC controller node with instruction on how to enable it while lowering capabilities of the eMMC controller from 8bits bus width to 4bits bus width, it's data pins 4 to 7 being shared with the SPI NOR controller pins. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> Link: https://lore.kernel.org/r/20200313090713.15147-4-narmstrong@baylibre.com
Diffstat (limited to 'arch/arm64')
-rw-r--r--arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi20
1 files changed, 20 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi b/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi
index e53cf03339d3..094ecf2222bb 100644
--- a/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi
@@ -326,6 +326,26 @@
vqmmc-supply = <&emmc_1v8>;
};
+/*
+ * EMMC_D4, EMMC_D5, EMMC_D6 and EMMC_D7 pins are shared between SPI NOR CS
+ * and eMMC Data 4 to 7 pins.
+ * Replace emmc_data_8b_pins to emmc_data_4b_pins from sd_emmc_c pinctrl-0,
+ * and change bus-width to 4 then spifc can be enabled.
+ */
+&spifc {
+ status = "disabled";
+ pinctrl-0 = <&nor_pins>;
+ pinctrl-names = "default";
+
+ w25q32: spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "winbond,w25q128fw", "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <104000000>;
+ };
+};
+
&uart_A {
status = "okay";
pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;